Proceedings for ICM 2006

Table of Contents

1. A 3 to 5 GHz UWB SiGe HBT Low Noise Amplifier.
Farid Touati

2. Adaptive Neural Network Model for SOI-MOSFET I-V Characteristics Including Self-Heating Effects.
Mohammad Azim Karami,Ali Afzali-Kusha

3. A 4x4 Tin Oxide Gas Sensor Array with on-chip signal pre-processing.
Bin Guo, Amine Bermak, Gui-Zhen Yan, Philip C.H Chan

4. A High Compliance Input and Output Regulated Body-Driven Current Mirror for Deep-Submicron CMOS.
Marc W. Murphy, Ezz I. El-Masry, Amro M. Elshurafa

5. A Simple Model for the Kink Effect for the Intrinsic p-channel Polysilicon Thin film transistors.
M. Jawaid Siddiqui and Abdur-Rahman F. Marshood

6. An Ultra-Wideband Low-Noise Amplifier for 3-5-GHz Wireless Systems.
Ahmad Saghafi and Dr. Abdolreza Nabavi

7. A Fully Integrated Range-Finder Based on the Line-Stripe Method.
Alireza Saberkari, Shahriar Baradaran Shokouhi

8. An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology.
A. Bouhraoua and Muhammad E. S. Elrabaa

9. A Mesochronous Technique for Communication in Network on Chips.
Mohsen Saneei, Ali Afzali-Kusha, and Zainalabedin Navabi

10. Low-latency Multi-Level Mesh Topology for NoCs.
Mohsen Saneei, Ali Afzali-Kusha, and Zainalabedin Navabi

11. Electronic Conception of a programmable hearing aid.
Nidhal Ben Amor, Hamadi Ghariani, Mongi Lahiani and Mounir Samet

12. Double-Edge triggered Level Converter Flip-Flop with Feedback.
Azam-Sadat Seyedi,Ali Afzali-Kusha

13. Improved Assertion Lifetime via Assertion-Based Testing Methodology.
Mohammad Riazati, Siamak Mohammadi, Zain Navabi

14. Finding low activity op-code sets using genetic computing.
Mohammad D. Mottaghi , Mohammad Riazati

15. Hot Block ring counter: A low power synchronous ring counter.
Mohammad D. Mottaghi , Ali Afzali Koosha , Zainalabedin Navabi

16. Synthesis of reversible circuits.
Jing Hu,Guangsheng Ma,Gang Feng

17. Experimental Evaluation of Three Concurrent Error Detection Mechanisms.
Alireza Vahdatpour, Mahdi Fazeli, Seyed Ghassem Miremadi

18. Accelerated Multi Grid Scheme for Substrate Coupling Modeling and Analysis.
Mohammad Azim Karami, Nasser Masoumi , Ebrahim Afjei

19. A MEMS Disk Resonator Based Oscillator.
Mostafa M. El Khouly, Yasseen Nada, Emad Hegazi, Hani F. Ragai, Moustafa Y. Ghannam

20. Translinear-C Function Generator.
Shahnaz Hasan and Iqbal A. Khan

21. Design of FIR Filters Using Identical Subfilters of Even Length.
S. M. Mortazavi Zanjani , S. Rahimian Omam, S. M. Fakhraie , O. Shoaei

22. Reconfigurable Low Power FIR Filter based on Partitioned Multipliers.
Habibullah Jamal, Farhat Abbas Shah, Muhammad Akhtar Khan

23. A Very Fast and Low Power Pseudo-Incrementer for Address Bus Encoder/Decoder.
Hadi Parandeh-Afshar, Ali Afzali-Kusha, and Ali Khakifirouz

24. An Optimal Structure for Implementation of Digital Filters.
S. Rahmanian, A. Nasiri Avanaki, E. Rahmani and S. M. Fakhraie

25. Exponentially Tapering Ground Wires for Elmore Delay Reduction in On Chip Interconnects.
M.A. Karami, Ali Afzali-Kusha

26. Artificial Neural Network Based Modeling of GaAs HBT and Power Amplifier Design for Wireless Communication System.
M.S.Alam, O. Farooq, Izharuddin and G.A. Armstrong

27. Design of Low Power, High Data Rate Modulator for Ultra-wideband Transmitters.
Abdolreza Nabavi

28. A Low Power Base-Band Circuit for Low-IF Wireless PAN Receivers.
Ramin Zanbaghi , Mojtaba Atarodi , Mohsen Moezzi , Armin Tajalli

29. A Crystal-Tolerant Fully Integrated Frequency Synthesizer For GPS Receivers: System Perspective.
Tarek M. H. Elesseily, Khaled M. Sharaf

30. Finding Agent-Based Energy-Efficient Routing in Sensor Networks using Parallel Genetic Algorithm.
E. Rahmani, S. M. Fakhraie, and M. Kamarei

31. Modified Leakage-Biased Domino Circuit with Low-Power and Low-Delay Characteristics.
Elaheh Rahmani, Zoha Pajouhi, Neda Kazemian-Amiri and Ali Afzali-Kusha

32. Interconnect-Efficient LDPC Code Design.
Aiman El-Maleh, Basil Arkasosy, M. Adnan Al-Andalusi

33. Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices.
Yassine Aoudni, Guy Gogniat, Jean-Luc Philippe, Mohamed Abid

34. Mems AD/DA Converters.
Amir J. Majid

35. CMOS Digitally Programmable Inductance.
Hussain Alzaher and Noman Tasadduq

36. A New Polyphase Current-Mode Filter Using Digitally-Programmable Current-Controlled Current-Conveyor.
S. M. Al-Shahrani and M. A. Al-Gahtani

37. First Order Current Mode Filters and Multiphase Sinusoidal Oscillators Using MOCCIIs.
I. A. Khan, P. Beg and M. T. Ahmed

38. A Slice-Based Automatic Hardware/Software Partitioning Heuristic.
H. Parandeh-Afshar, A. Tootoonchian, M. Yousefpour, O. Fatemi, and M. Hashemi

39. Synthesis of MVL Functions Part I: The Genetic Algorithm Approach.
Bambang A. B. Sarif, Mostafa Abd-El-Barr

40. Synthesis of MVL Functions Part II: The Ant Colony Optimization Approach.
Mostafa Abd-El-Barr, Bambang A. B. Sarif

41. Scalability Evaluation of a Hybrid Routing Architecture for Multi-FPGA Systems.
Mohammed A. S. Khalid and Viktor Salitrennik

42. Coding for Minimizing Energy in VLSI Interconnects.
K S Sainarayanan, J V R Ravindra, M B Srinivas

43. Soft-Core Processors for Embedded Systems.
Jason G. Tong, Ian D. L. Anderson and Mohammed A. S. Khalid

44. A Check pointing Technique for Rollback Error Recovery in Embedded Systems.
Mohesen Bashiri, Seyed Ghassem Miremadi and Mahdi Fazeli

45. On-line Testing and Diagnosis of Micro-controller.
Khaled Elshafey, Ahmed Elhosiny

46. Introducing Energy and Area Estimation in HW/SW Design Flow Based on Transaction Level Modeling.
Muhammad Omer Cheema, Omar Hammami

47. Low Power Area Efficient High Data Rate 16-bit AES Crypto Processor.
Habibullah Jamal, Sheikh M Farhan and Shoab A Khan

48. Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine.
A. Bouhraoua

49. A Fixed Delay Infinite-Bit Split Adder Architecture and Its Application in Real-Time Image Processing.
Amjad Fuad Hajjar

50. A Portable Clock Recovery Circuit (CRC) For Systems-On-Chip Serial Data Communication.
Muhammad E. S. Elrabaa

51. Separating Modeling and Simulation Aspects in Hardware/Software System Design.
J. Lapalme, E.M. Aboulhamid , G. Nicolescu, F. Rousseau

52. A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links.
Muhammad E. S. Elrabaa

53. General Two-Party Oblivious Circuit Evaluation.
Sufyan T. Faraj

54. Smooth Boundary Point Adaptive Quantizer for on-chip Image Compression.
Shoushun Chen, Amine Bermak, Wang Yan, Dominique Martinez

55. A Quantitative Study on Layer-2 Packet Processing on a General Purpose Processor.
Mostafa Salehi, Ramin Rafati, and Sied Mehdi Fakhraie

56. Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption.
Seyed E. Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam

57. Frequency Independent Phase Shifter.
Munir A. Al-Absi

58. Prediction of Spectral Regrowth of Quasi-Memoryless Fifth-order RF Amplifiers under Multitone Excitation.
N. Boulejfen, A. Harguem, and F. M. Ghannouchi

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