|
COE 202 - Digital Logic Design Term 161 - Fall 2016 |
|
|
Office: Building 22, Room 328, Phone: 4642 Syllabus | Lectures | Assignments | Tools Announcements Final Exam: Wednesday, January 11, at 7 PM, Building 11, Room 130 Quiz 7: Sequential Circuit Design, Tuesday, January 3 Quiz 6: Analysis of Clocked Sequential Circuits, Tuesday, December 20 Quiz 5: Arithmetic Circuits, Sunday, November 27 Quiz 4: The Karnaugh Map, Tuesday, November 8 Quiz 3: Additional Gates, Tuesday, November 1 Quiz 2: Boolean Algebra and Logic Gates, Thursday, October 13 Quiz 1: Number Systems and Binary Codes, Tuesday, October 4 Exam 1: Saturday, October 22, at 1 PM, Building 22, Room 119 Exam 2: Saturday, December 3, at 1 PM, Building 22, Room 132 Assistant Ibrahim Al-Beladi Email: s201224780@kfupm.edu.sa Any question related to grading should be directed to the teaching assistant Textbook Alan B. Marcovitz, Introduction to Logic Design, third edition, McGraw Hill, 2010 Catalog Description Introduction to information representation and number systems. Boolean algebra and switching theory. Manipulation and minimization of completely and incompletely specified Boolean functions. Propagation delay, timing diagrams. Combinational circuit design using multiplexers, decoders, comparators, and adders. Sequential circuit analysis and design, basic flip-flops, clocking and timing diagrams. Registers, counters, ROMs, PALs, PLAs, and FPGAs. Introduction to Verilog. Prerequisite: PHYS 102. Course Learning Outcomes
Academic Honesty View important information on academic honesty Exam Schedule Exam 1: Saturday, October 22, at 1 PM Exam 2: Saturday, December 3, at 1 PM Final Exam: Wednesday, January 11, at 7 PM Previous Exams Grading Assignments & Quizzes: 20% Major Exam I: 20% Major Exam II: 25% Final Exam: 35%
|
|
| Last Updated: Friday January 06, 2017, by Dr. Muhamed Mudawar |