Verilog Assigment 1: Due, Thursday, November 10 (during class time)

Modeling Boolean functions

Verilog Assigment 2: Due, Thursday, January 5 (during class time)

Two problems: Modeling an ALU and a Sequential Circuit

Can be done in groups of two students

Problem Set 1: Not Graded

Chapter 1: Exercises 1, 2, 3, 4, 11, 12

Answers to selected exercises are available in appendix B.1 for chapter 1

Problem Set 2: Not Graded

Chapter 2: Exercises 2(a, d, g), 3, 4, 5b, 7, 8(a, d, f), 11, 12, 14, 21(c, g, j), 23b, 24c, 25c

Answers to selected exercises are available in appendix B.2 (for chapter 2)

Problem Set 3: Not Graded

Chapter 2: Exercises 18, 19, 21, 26, 27

Answers to selected exercises are available in appendix B.2

Problem Set 4: Not Graded

Chapter 3: Exercises 1(b, d), 2(b, e, i, m, n), 3, 5(c, f), 7(a, d, i), 9(c, f, i, n), 10(b), 11(a, e, h, j)

Answers to selected exercises are available in appendix B.3 (for chapter 3)

Problem Set 5: Not Graded

Chapter 1: Exercises 6, 7, 8, 9, 10

Answers to selected exercises are available in appendix B.1

Problem Set 6: Not Graded

Chapter 5: Exercises 2, 7, 9, 12, 18, 21

Answers to selected exercises are available in appendix B.5

Problem Set 7: Not Graded

Chapter 6: Exercises 1b, 4c, 7b, 9c

Chapter 6 Test, pages 412 - 414

Answers to selected exercises are available in appendix B.6

Chapter test answers are available in appendix C.6

Problem Set 8: Not Graded

Chapter 7: Exercises 2a, 2f, 3c, 4b, 7a, 8b, 16b, 16f, 16k, 16l

Chapter 7 Test, pages 491 - 492

Answers to selected exercises are available in appendix B.7

Chapter 7 test answers are available in appendix C.7