TEACHING MATERIAL

  1. Computing System Fundamentals/Trends, Review of Performance Evaluation, and ISA Design (3rd Edition: Chapters 1 and 2)    Reading: Designing for Power: Intel Leadership in Power Efficient Silicon and System Design, www.intel.com/technology.

  2. Review of Instruction Pipelining (In  Appendix A)

  3. Exploiting Instruction level Parallelism (Third Edition:  Chap. 3.1 and 4.1)

  4. Dynamic Hardware-Based Instruction Pipeline Scheduling (In Third Edition: Appendix A.8 and Chapter 3.2, 3.3)

  5. Reduction of Data Hazards Stalls with Dynamic Scheduling (Third Edition: Chapter 3.6,  3.7, and 4.3)

  6. Reduction of Control Hazards (Branch) Stalls with Dynamic Branch Prediction (3rd Edition: Static Pred.  in Ch. 4.2   Dynamic Pred. in Ch.  3.4, BTB in Ch. 3.5)

  7. Multiple Instruction Issue and scheduling, Superscalar dynamic execution, speculative execution, and Dual-Core Chip-Multiprocessor (CMP) Architectures (3rd Edition: Chapter 3.6, 3.7, 4.3)

  8. Static Compiler Optimization Techniques and Vector Processing (3rd Edition: Chapter 4.4, vector processing: Appendix G)

  9. The Memory Hierarchy & Cache (3rd Edition Chapter 5.1-5.4)

  10. Input/Output & System Performance Issues (3rd Edition: Chapter  7.1-7.3,   7.7, 7.8)

  11. Main Memory, Mainstream Computer System Components (3rd Edition: Chapter  5.8, 5.9)

  12. Virtual Memory

  13. Multiprocessors

  14. Cache Coherency

  15. Directory Coherency

  16. Multiprocessor Synchronization

  17. Review

GRADING

  1. Homework 1 and Solution

  2. Homework 2 and solution

  3. Exam I with its solution

  4. Homework 3 and solution

  5. Homework 4 with solution

  6. Exam II with its solution

  7. Grades

REFERENCE PRESENTATIONS

  1. Introduction to computer architecture

  2. Performance

  3. Instruction set architecture

  4. Instruction set examples

  5. Pipelining and hazards

  6. MIPS R4000 and ILP

  7. Superscalar and VLIW

  8. Compiler and hardware support for ILP

  9. Memory Hierarchy and Cache Design

  10. Reducing Cache Misses

  11. Reduce Miss Penalty and Hit Time

  12. Main Memory

  13. Virtual Memory and the Alpha 21064 Memory Hierarchy

  14. Networks and Interconnect

  15. Interconnection Networks

 

REVIEWING MATERIAL FROM UNDERGRADUATE LEVEL

  1. Introduction to Computer Architecture
  2. Performance of Computers
  3. Tutorial on SPIM Processor Simulator
  4. MIPS ISA I
  5. MIPS ISA II
  6. MIPS ISA III
  7. MIPS ISA IV
  8. Computer Arithmetics I (Signed and unsigned representation)
  9. Computer Arithmetics II (Integer multiply, divide, and floating-point)
  10. Introduction to DataPath
  11. Single Cycle DataPath
  12. Multi-Cycle DataPath
  13. Instruction Pipelining I
  14. Instruction Pipelining II
    15.
  15. Instruction Pipelining III
  16. Memory System I
  17. Memory System II
  18. Bus systems
  19. I/O system
  20. Multiprocessors