COE 501 Lectures

Computer Architecture

 

Muhamed F. Mudawar

mudawar@kfupm.edu.sa

Office: Building 22, Room 328, Phone: 4642

COE 501 Home | Syllabus | Exercises | Tools and Manuals

 

Lecture Presentations

Introduction to Computer Architecture

Performance

IC Manufacturing, Cost, Power, and Dependability

Instruction Set Principles and Architectures

Main Memory

Cache Memory

Cache Optimization

Virtual Memory

Instruction Pipelining: Basic and Intermediate Concepts

Advanced Pipelining

Static Instruction Level Parallelism and VLIW

Multiprocessors and Thread-Level Parallelism

Data-Level Parallelism in Vector, SIMD, and GPU Architectures

 

Additional Reading

Introduction to Integrated Circuit Technology (Jones)

Survey of Instruction Set Architectures (H&P Book, Appendix K)

The Microarchitecture of Superscalar Processors (Smith and Sohi)

Hardware and Software for VLIW and EPIC (H&P Book, Appendix H)

Why On-Chip Cache Coherence is Here to Stay (Martin, Hill, and Sorin)

Niagara: A 32-Way Multithreaded Sparc Processor (Kongetira, Aingaran, and Olukotun)

 

  Last Updated: Wednesday January 26, 2022, by Dr. Muhamed Mudawar