TOPICS BREAKDOWN
-
|
Unit I |
|
|
Number System and
Codes |
PDF |
|
1 |
Introduction. Information
Processing, and
representation. Digital vs
Analog quantities. |
Download |
|
2 |
Number Systems. Binary, Octal
and Hexadecimal #’s |
Download |
|
3 |
Number System Arithmetic.
Binary arith (Addition,
Subtraction & Multiplication).
Arith in other systems. |
Download |
|
4 |
Number base conversion (Dec to
Bin, Oct, and Hex, General).
Conv (Bin, OCT, Hex) |
Download |
|
5 |
Binary Storage & Registers.
Signed Binary Number representation, Signed
Mag, R’s &(R-1)’s
Complement |
Download |
|
6 |
Signed Binary Addition and
Subtraction. R’s Complement. Signed Binary Addition
and Subtraction. (R-1)’s Complement |
Download |
|
7 |
Codes. BCD, Excess-3, Parity
Bits, ASCII & Uni-Codes
|
Download |
|
Unit II |
|
|
Binary Logic &
Gates |
PDF |
|
1 |
Binary logic and gates, Boolean
Algebra, Basic identities of Boolean algebra.
Algebraic manipulation, Complement of a
function. |
Download |
|
2 |
Canonical and Standard forms,
Minterms and Maxterms,
Sum of products and Products of Sums. |
Download |
|
3 |
Physical properties of gates: fan-in, fan-out,
propagation delay. Timing diagrams. Tri-state
drivers. |
Download |
|
4 |
Map method of
simplification: Two-, Three-, and
Four-variable K-Map. |
Download |
|
5 |
Map manipulation:
Essential prime implicants,
Non-essential prime implicants,
Simplification procedure, POS simplification, Don’t
care conditions and simplification, Five, and
Six-variable K-Map. |
Download |
|
6 |
Universal gates; NAND, NOR gates:
2-level implementation. Multilevel Circuits. |
Download |
|
7 |
Exclusive-OR (XOR) and
Equivalence (XNOR) gates, Odd and Even Functions,
Parity generation and checking. |
Download |
|
Unit III |
|
|
Combinational Logic |
PDF |
|
1 |
Combinational Logic, Design
Procedure & Examples. |
Download |
|
2 |
Half and Full Adders, Half and
Full Subtractor, Ripple
Carry Adder design and
delay
analysis |
Download |
|
3 |
Carry Look-Ahead Adder,
Binary Adder-Subtractor.
BCD Adder, Binary Multiplier |
Download |
|
4 |
MSI parts. Decoders, Decoder
expansion, combinational logic implementation using
decoders, Encoders & Priority Encoders |
Download |
|
5 |
Multiplexers, Function
Implementation using multiplexers,
Demultiplexers |
Download |
|
6 |
Magnitude Comparator. |
Download |
|
7 |
Examples of MSI designs |
Download |
Unit IV |
|
|
Sequential Circuits |
PDF |
|
1 |
Sequential Circuits:
Latches,
Clocked latches: SR , D, T and JK. Race problem in
clocked JK-Latch. Function & Excitation Tables
of clocked latches: SR, D, and JK. |
Download |
|
2 |
Flip-Flops:
Master-Slave,
T-FF. Function & Excitation Tables of T-FF.
Asynchronous/Direct
Clear and Set Inputs. Setup, Hold |
Download |
|
3 |
Sequential Circuit Design: Excitation
Tables. Design procedure, State diagrams and state
tables. |
Download |
|
4 |
Sequential Circuit Analysis: Input
equations, State table.
|
Download |
|
5 |
Mealy vs.
Moore models of
FSMs. Examples. |
Download |
|
Unit V |
|
|
Registers &
Counters |
PDF |
|
1 |
Registers, Registers with parallel load, Shift
Registers. Bi-directional shift register. |
Download |
|
2 |
Synchronous Binary Counters: Up-Down
Counters.
|
Download |
|
3 |
Counters with Parallel load,
enable, synchronous clear and asynchronous clear.
Use of available counters to build counters of
different count. |
Download |
|
4 |
Other counters: Ripple
Counter, Arbitrary Count Sequence. |
Download |
|
|
|
|
|
|
Unit VI |
|
|
Memory &
PLDs |
PDF |
|
1 |
Memory devices: RAMs &
ROMs . Combinational
Circuit Implementation with ROM |
Download |
|
2 |
Programmable Logic Devices:
PLAs, PALs,
FPGA’a |
Download |
|
|
|
|
|
DOWNLOADING ALL COURSE MATERIAL
SOLUTION TO SELECTED TOPICS
HOMEWORK, QUIZ, EXAM AND THEIR SOLUTIONS
- Homework
1 and its
solution
- Homework
2 and its
solution
- Homework 3 and its
solution
- Homework 4 and its
solution
- Quiz 1
and solution
- Exam 1
and its solution
- Exam 2 and
its solution
- Quiz 2
and solution
- Quiz 3 and
solution
SOFTWARE TOOLS FOR LOGIC DESIGN
A presentation was given to the students on how to use CAD tools
for logic design (see lecture
topics)
Students are encouraged to form teams of two for working on the
course project listed here:
Design of
an 8-Bit Magnitude Comparator using Logisim
Students are given the chance to improve their Exam II
grades based on timely submission of their project report. The report
must be written in a way to meet the Engineering Design Aspect at
200-level (see Guideline here). The email of Mr. Abbasi is:
Ameer Ahmed Abbasi
[ameer_abbasi@hussan.edu.sa]
Mr. Ameer Ahmed Abbasi
will be available for helping the students on Logisim on Monday, from 8
am to 9 am, 5th of January, 2008.
Project Supporting Material
Logisim version 2.1.5
Guide to Logisim
Website for Logisim
Introductory Guidelines to Engineering Design
How to
address Engineering Design in the Porject
Guidelines to Engineering Design
Evaluation of Student Design is as follows:
| |
|
|
|
|
S.No. |
Student ID |
Documentation |
Circuit |
|
1 |
200669580 |
Fair |
Fair |
|
2 |
200576510 |
Vey Good |
Excellent |
|
3 |
200670780 |
Vey Good |
Excellent |
|
4 |
200628120 |
Poor |
Very Poor |
|
5 |
200630980 |
Very Good |
Excellent |
|
6 |
200684180 |
Excellent |
Excellent |
|
7 |
200638480 |
Excellent |
Excellent |
|
8 |
200639380 |
Fair |
Excellent |
|
9 |
200645960 |
Very Poor |
Poor |
|
10 |
200646060 |
Poor |
Excellent |
|
11 |
200650940 |
Good |
Very Good |
|
12 |
200652600 |
Fair |
Excellent |
|
13 |
200660760 |
Very Poor |
Good |
|
14 |
200667040 |
Good |
Excellent |