COE 202 Lectures
Digital Logic Design
Aiman H. El-Maleh
Office: Building 22, Room 405-7, Phone: 2811
Schedule and Office Hours
COE 202 Home | Syllabus | Exercises | Tools | Course Resources
Unit 1: Data Representation
Unit 2: Binary and Logic Gates
Unit 3: Standard and Canonical Forms
Unit 4: K-Map Simplification
Unit 5: Other Gate Types
Introduction to Verilog: Lecture 1
Unit 6: Combinational Circuit Design
Unit 7: Arithmetic Functions and Circuits
Unit 8: Functions and Functional Blocks
Introduction to Verilog: Lecture 2
Unit 9: Sequential Circuits Analysis and Design
Unit 10: Registers and Counters
Introduction to Verilog: Lecture 3