COE

EE 200 Digital Logic Circuit Design

Office Hours before final exam - Thursday Dec 24th 10:30-12:00 (Rm 22-420)

Course Syllabus:

Click here for course syllabus.

Lecture Notes:

Students are responsible for the material in the book and that explained in class. The class notes are just "notes";

Unit 1 - Digital Systems and Binary Numbers - notes - summary on signed numbers and overflow; timing diagrams.
Unit 2 - Boolean Algebra and Logic Gates - Gate Level Minimization - notes
Unit 3 - Combination Logic - notes
Unit 4 - Synchronous Sequential Logic - notes; Mealy vs Moore with timing diagrams; review problems
Unit 5 - Registers and Counters - notes
Unit 6 - Memory and Programmable Logic - notes

Exam Dates:

Major Exam1: Tuesday Oct 13th, 2015 - 18:30-20:00 Rm 59-1007.
Major Exam2: Tuesday Nov 10th, 2015 - 18:30-20:30 Rm TBD
Final Exam: Monday Dec 28th, 7:00 pm - Location - Bldg. 10.

Assignments:

Homework #1: due date Sept 13th, 2015. Solution Key.
Homework #2: due date Oct 4th, 2015. Solution Key.
Homework #3: due date Nov 1st, 2015. Solution Key.
Homework #4: due date Nov 26th, 2015. Solution Key.

Quizzes and Major Exams:

Quiz01: Sept 1st, 2015. Solution given in class.
Quiz02: Sept 15th, 2015. Solution given in class.
Major Exam 1: Tuesday Oct 13th, 2015 - Solved in class (on the board) on Thursday Oct 15th.
Quiz03: Oct 25th, 2015. Solved in class.
Quiz04: Nov 5th, 2015, Solved in class.
Quiz05: Nov 12th, 2015, Solved in class.
Quiz06: Nov 17th, 2015, Takehome.
Quiz07: Dec 13th, 2015, Solved in class. Refer to class notes on Registers.

Check Your Status:

To check your marks for quizzes and homework as well as yours exams, bonus, etc. click here.

For attendance - click here.

Announcements:

Link for the LogiSim tool.
You can also pick this K-Map program for simplifying functions.

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