Week

Course Topics

Reading

1

Introduction to computer architecture, ISA versus organization, components, abstraction, technology improvements, chip manufacturing process.

Chapter 1

2-4

Instruction set design, RISC design principles, MIPS registers, instruction formats, arithmetic instructions, immediate operands, bit manipulation, load and store instructions, byte ordering, addressing modes, flow control instructions, pseudo-instructions, procedures and runtime stack, call and return, MIPS register conventions, alternative IA-32 architecture.

Sections 2.1 – 2.9

Sections 2.13, 2.15 – 2.18

Sections 3.2 – 3.3

Appendix A.9 – A.10

5

CPU performance and metrics, CPI, performance equation, MIPS as a metric, Amdahl’s law, benchmarks and performance of recent Intel processors.

Chapter 4

6-7

Integer multiplication, integer division, floating point representation, IEEE 754 standard, normalized and de-normalized numbers, zero, infinity, NaN, FP comparison, FP addition, FP multiplication, rounding and accurate arithmetic, FP instructions in MIPS.

Sections 3.4 – 3.6

Sections 3.8 – 3.9

8-9

Designing a processor, register transfer logic, datapath components, clocking methodology, single-cycle datapath, main control signals, ALU control, single-cycle delay, multi-cycle versus single-cycle instruction execution.

Sections 5.1 – 5.5

10

Pipelining versus serial execution, MIPS 5-stage pipeline, pipelined datapath, pipelined control, pipeline performance.

Sections 6.1 – 6.3

11

Pipeline hazards, structural hazards, data hazards, stalling pipeline, forwarding, load delay, compiler scheduling, hazard detection, stall and forwarding unit, control hazards, branch delay, dynamic branch prediction, branch target and prediction buffer.  

Sections 6.4 – 6.6

12-13

Cache memory design, locality of reference, memory hierarchy, DRAM and SRAM, direct-mapped, fully-associative, and set-associative caches, handling cache miss, write policy, write buffer, replacement policy, cache performance, CPI with memory stall cycles, AMAT, two-level caches and their performance, main memory organization and performance.

Sections 7.1 – 7.3

Sections 7.5 – 7.6

14-15

Introduction to parallel architectures