COE 308 - Spring 2009

Computer Architecture


Muhamed F. Mudawar

Office: Building 22, Room 328, Phone: 4642

Schedule and Office Hours

Syllabus | Lectures | Assignments | Tools and Manuals | Fall 2008


Final Exam: Wednesday, June 24, 7 PM, Building 23, Room 011

Quiz 5 on Single-Cycle CPU Design: Saturday, May 23

Quiz 4 on Performance and Metrics: Monday, May 11

Quiz 3 on Integer Multiplication and Division: Monday, May 4

Major Exam 1: Sunday, April 12, 7 pm, Building 24, Room 120

Covers: introduction, MIPS Instruction Set, MIPS Assembly Language, & Floating-Point

Quiz 2 on MIPS Instruction and Assembly Language: Wednesday, March 25

Quiz 1 on Computer Abstractions and Technology: Wednesday, March 11


Ammar Meer


Any question related to grading should be directed to the teaching assistant


David A. Patterson and John L. Hennessy Computer Organization & Design, The Hardware/Software Interface, Third Edition, Morgan Kaufmann Publishers, 2005. ISBN: 1-55860-604-1.

Course Objectives

  • In-depth understanding of the inner-workings of modern computer systems, their evolution, and tradeoffs present at the hardware-software interface.

  • Understanding the design process of a modern computer system. This includes the design of the processor datapath, control, memory system, and I/O subsystem.

Academic Honesty

View important information on academic honesty

Exam Schedule

Exam 1: Sunday, April 12, 7 PM, Building 24, Room 120

Exam 2: Tuesday, May 26, 7 PM, Building 24, Room 121

Final Exam: Wednesday, June 24, 7 PM, Building 23, Room 011

Sample Exams

Exam 1 - Spring 2008

Exam 2 - Fall 2008

Final Exam - Fall 2008


Homework & Quizzes: 10%

Projects: 25%

Major Exam I: 20%

Major Exam II: 20%

Final Exam: 25%

  • Homework should be submitted at the beginning of class time in the specified due date.

  • Late homework is not accepted, especially if the solution is posted online.

  • Late projects are accepted, but will be penalized 5% for each late day for a maximum of 5 late days.


    Course Topics and Lecture Breakdown by Week



    Course Topics



    Introduction to computer architecture, ISA versus organization, components, abstraction, technology improvements, chip manufacturing process.

    Chapter 1


    Instruction set design, RISC design principles, MIPS registers, instruction formats, arithmetic instructions, immediate operands, bit manipulation, load and store instructions, byte ordering, addressing modes, flow control instructions, pseudo-instructions, procedures and runtime stack, call and return, MIPS register conventions, alternative IA-32 architecture.

    Sections 2.1 – 2.9

    Sections 2.13, 2.15 – 2.18

    Sections 3.2 – 3.3

    Appendix A.9 – A.10


    CPU performance and metrics, CPI, performance equation, MIPS as a metric, Amdahl’s law, benchmarks and performance of recent Intel processors.

    Chapter 4


    Integer multiplication, integer division, floating point representation, IEEE 754 standard, normalized and de-normalized numbers, zero, infinity, NaN, FP comparison, FP addition, FP multiplication, rounding and accurate arithmetic, FP instructions in MIPS.

    Sections 3.4 – 3.6

    Sections 3.8 – 3.9


    Designing a processor, register transfer logic, datapath components, clocking methodology, single-cycle datapath, main control signals, ALU control, single-cycle delay, multi-cycle versus single-cycle instruction execution.

    Sections 5.1 – 5.5


    Pipelining versus serial execution, MIPS 5-stage pipeline, pipelined datapath, pipelined control, pipeline performance.

    Sections 6.1 – 6.3


    Pipeline hazards, structural hazards, data hazards, stalling pipeline, forwarding, load delay, compiler scheduling, hazard detection, stall and forwarding unit, control hazards, branch delay, dynamic branch prediction, branch target and prediction buffer.  

    Sections 6.4 – 6.6


    Cache memory design, locality of reference, memory hierarchy, DRAM and SRAM, direct-mapped, fully-associative, and set-associative caches, handling cache miss, write policy, write buffer, replacement policy, cache performance, CPI with memory stall cycles, AMAT, two-level caches and their performance, main memory organization and performance.

    Sections 7.1 – 7.3

    Sections 7.5 – 7.6


    Introduction to parallel architectures



  •   Last Updated: Saturday October 03, 2009, by Dr. Muhamed Mudawar