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Muhamed F. Mudawar
mudawar@kfupm.edu.sa
Office: Building 22, Room 328, Phone: 4642
Schedule and
Office Hours
Syllabus |
Lectures |
Assignments |
Spring 2008
Announcements
Final Exam: Saturday, February 7, at 7:30 AM,
Building 22, Room 119
Major Exam 2: Monday, January 12 at 7 pm, Building
24, Room 174
Quiz 2 on Integer Multiplication and Division:
Monday, December 22
Major Exam 1: Monday, November 24 at 7 pm, Building
24, Room 120
Quiz 1 on MIPS Instruction Set: Saturday, November
1st
Assistant
Mohammad Adnan Khan
Email:
adnankhan87@gmail.com
Any question related to grading should be directed to the teaching assistant
Textbook
David A. Patterson and John L. Hennessy Computer Organization & Design, The Hardware/Software Interface,
Third Edition, Morgan Kaufmann Publishers, 2005. ISBN: 1-55860-604-1.
Course Objectives
-
Understanding the design process
of a modern computer system. This includes the design of the processor
datapath, control, memory system, and I/O subsystem.
Academic Honesty
View
important information on academic honesty
Exam
Schedule
Exam 1:
Monday, November 24, at 7
PM, Building 24, Room 120
Exam 2: Monday, January 12, at
7 PM, Building 24, Room 174
Final Exam: Final Exam:
Saturday, February 7, at 7:30 AM, Building 22, Room 119
Grading
Assignments & Quizzes: 10%
Projects: 25%
Major Exam I: 20%
Major Exam II: 20%
Final
Exam: 25%
Assignments should be submitted
at the beginning of class time in the specified due date.
Late assignments are not
accepted, especially if the solution is discussed in class.
Late projects are
accepted, but will be penalized 5% for each late day for a maximum of 5
late days
Software
Tools used in Projects
MARS Simulator: runs MIPS-32 assembly
language programs
MARS
homepage, MARS paper,
Sample Program (Fibonacci.asm)
Appendix A in Patterson and
Hennessy Book
Logisim Simulator:
educational tool for designing and simulating CPUs
Logisim homepage
Manuals
MIPS32 Architecture
for Programmers, Volume I: Introduction to the MIPS32 Architecture,
MIPS Technologies Inc, Revision 2.50, July 2005.
MIPS32
Architecture for Programmers, Volume II: The MIPS32 Instruction Set,
MIPS Technologies Inc, Revision 2.50, July 2005.
MIPS32
Architecture for Programmers, Volume III: The MIPS32 Privileged Resource
Architecture, MIPS Technologies Inc, Revision 2.50, July 2005.
Course
Topics and Lecture Breakdown by Week
Week |
Course Topics |
Reading |
1 |
Introduction to computer
architecture, ISA versus organization, components, abstraction,
technology improvements, chip manufacturing process. |
Chapter 1 |
2-4 |
Instruction set design,
RISC design principles, MIPS registers, instruction formats,
arithmetic instructions, immediate operands, bit manipulation,
load and store instructions, byte ordering, addressing modes,
flow control instructions, pseudo-instructions, procedures and
runtime stack, call and return, MIPS register conventions,
alternative IA-32 architecture. |
Sections 2.1 – 2.9
Sections 2.13, 2.15 – 2.18
Sections 3.2 – 3.3
Appendix A.9 – A.10 |
5 |
CPU performance and
metrics, CPI, performance equation, MIPS as a metric, Amdahl’s
law, benchmarks and performance of recent Intel processors. |
Chapter 4 |
6-7 |
Integer multiplication,
integer division, floating point representation, IEEE 754
standard, normalized and de-normalized numbers, zero, infinity,
NaN, FP comparison, FP addition, FP multiplication, rounding and
accurate arithmetic, FP instructions in MIPS. |
Sections 3.4 – 3.6
Sections 3.8 – 3.9 |
8-9 |
Designing a processor,
register transfer logic, datapath components, clocking
methodology, single-cycle datapath, main control signals, ALU
control, single-cycle delay, multi-cycle instruction execution,
multi-cycle implementation, CPI in a multi-cycle CPU. |
Sections 5.1 – 5.5 |
10 |
Pipelining versus serial
execution, MIPS 5-stage pipeline, pipelined datapath, pipelined
control, pipeline performance. |
Sections 6.1 – 6.3 |
11 |
Pipeline hazards,
structural hazards, data hazards, stalling pipeline, forwarding,
load delay, compiler scheduling, hazard detection, stall and
forwarding unit, control hazards, branch delay, dynamic branch
prediction, branch target and prediction buffer. |
Sections 6.4 – 6.6 |
12-13 |
Cache memory design,
locality of reference, memory hierarchy, DRAM and SRAM,
direct-mapped, fully-associative, and set-associative caches,
handling cache miss, write policy, write buffer, replacement
policy, cache performance, CPI with memory stall cycles, AMAT,
two-level caches and their performance, main memory organization
and performance. |
Sections 7.1 – 7.3
Sections 7.5 – 7.6 |
14 |
Virtual memory, address
mapping, page table, handling a page fault, TLB, virtual versus
physical caches, overlapped TLB and cache access. |
Section 7.4 |
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