Fetch Control Sequence 

In the fetch-execute cycle, the CPU goes in the cycle of reading an instruction, then executing it and repeating the process until it is terminated. The Program Counter holds the address of the next instruction to be fetched from memory. The Instruction Register is used to hold the fetched instruction to be executed. In the fetch phase, the CPU reads the instruction from memory based on the address given in the PC and stored the read instruction in the IR. Then, the program counter is incremented by the size of the fetched instruction. In the execution phase, the instruction is executed which involves decoding the instruction to know its type, fetching the operands of the instruction if necessary and finally executing the instruction.

For simplicity, let us assume that each instruction occupies one memory location so that we increment the program counter by 1. The fetch-execute process can be summarized as follows:
1. Fetch the content of memory location pointed by PC and load it into IR; IR ← [PC]
2. Increment the content of PC by 1; PC← PC + 1
3. Execute the instruction based on the content of IR.

The fetch control sequence of the single-bus CPU is illustrated next. Each control sequence Ti corresponds to one or more clock cycles. In order to fetch an instruction from memory in the single-bus CPU, this requires three control steps and at least three clock cycles as shown below:

Control Sequence Active Signals
T1 PCout, MARin, Read, ALU (C=B+1), Zin
T2 Zout, PCin, WMFC
T3 MDRout, IRin

In T1, the content of the program counter is put on the bus by activating the signal PCout. The ALU is controlled to perform the operation C=B+1 i.e. to increment the B input which is connected to the bus (which contains the PC content). The MAR will capture the content of the bus (which is the content of PC) by activating the MARin signal and the Z register will capture the output of the ALU (which is the incremented value of the PC) by activating the Zin signal. Both the MAR and PC will capture on the falling-edge of the clock. Also, the read signal is activated to request the memory to perform a read operation. Note that T1 will finish in one clock cycle.

In T2, the content of the Z register is put on the bus by activating the Zout signal. The PC is loaded by the content of the bus (which is the content of the Z register which is PC+1) by activating the signal PCin. The Wait Memory Function Complete (WMFC) signal is activated to inform the control unit to remain in T2 until the memory finishes the requested read operation. This is why T2 make take more than one clock cycle depending on the number of clock cycles needed by the memory to finish the read operation. After the memory finishes its function, it will put the requested value (in this case the instruction) in the MDR.

In T3, the content of the MDR (which contains the read instruction) is put on the bus by activating the signal MDRout. The IR is loaded with the fetched instruction by activating the signal IRin. This control step will take one clock cycle. Thus, at the end of this control step the fetch cycle will be complete. The fetched instruction is in the IR and the PC has been incremented to point to the next instruction to be fetched.

Fig. m300120.1 Fetch Control Sequence for Single-Bus CPU