Single-Bus CPU Design 

In the following, we show the data path structure of a single-bus CPU design. The data path is assumed to be 16-bit wide. It consists of four general purpose registers, namely R1, R2, R3, and R4. It also contains the Program Counter (PC) and the Instruction Pointer (IP) registers. In addition, it contains an Arithmetic and Logic Unit (ALU). Note that one input of the ALU is directly connected to the bus, while the second input is connected to register Y which is a temporary register to hold the first operand (A). The result of the ALU is stored temporarily in register Z as it cannot connect directly to the bus. Remember that the bus can hold a single value at a time. Thus, it cannot be holding the value of the B operand of the ALU and in the same time hold the ALU result as this will lead to bus contention (conflict).

The data path also contains two registers to interface with the memory subsystem, namely the Memory Address Register (MAR) and the Memory Data Register (MDR). The MAR is connected to the address bus and the MDR is connected to the data bus.

Fig. m300118.1 Single Bus CPU

Note that all the registers connected to the CPU bus are connected through tri-state buffers and have output control signals (OUT Signals). This applies to all the registers except the MAR and the Y register. The output of both registers is not connected to the bus. Also, all the registers are controlled by capture signals (IN signals) that capture on the falling-edge of the clock.