ICS 233 - Term 092 - Spring 2010
Computer Architecture & Assembly Language


Muhamed F. Mudawar


Office: Building 22, Room 328, Phone: 4642

Schedule and Office Hours

Syllabus | Lectures | Assignments | Tools and Manuals | Fall 2009


Final Exam: Monday, June 14, 7:30 am, Room 22-134 (Instruction Sheet)

Final Exam Topics: Processor Design, Pipelining, Caches, and Performance

Exam 2: Saturday, May 22, 6:30 pm, Build 23, Room 014 (Instruction Sheet)

Quiz 5 on Single-Cycle Processor: Saturday, May 22

Quiz 4 on Performance: Monday, May 3

Exam 1: Saturday, April 10, 6 pm, Building 23, Room 014

Quiz 3 on Floating-Point: Wednesday, April 7

Quiz 2 on MIPS Instruction Set Architecture: Monday, March 22

Quiz 1 on Computer Technology and Data Representation: Monday, March 8


Abdullah Al-Amoudi

Email: a_a_ba@hotmail.com

Questions related to assignments and grading should be directed to the teaching assistant


David A. Patterson and John L. Hennessy, Computer Organization & Design, The Hardware/Software Interface, Third Edition, Morgan Kaufmann Publishers, 2005. ISBN: 1-55860-604-1.

Robert L. Britton, MIPS Assembly Language Programming, Pearson Prentice Hall, 2004.

Course Objectives

Towards the end of this course, students should be able to:

Describe the instruction set architecture of a MIPS processor

Analyze, write, and test MIPS assembly language programs

Describe the organization/operation of integer and floating-point arithmetic units

Design the datapath and control of a single-cycle processor

Design the datapath and control of a pipelined processor and handle hazards

Describe the organization/operation of memory and caches

Analyze the performance of processors and caches

Academic Honesty

View important information on academic honesty

Exam Schedule

Exam 1: Saturday, April 10, 6 pm, Building 23, Room 014

Exam 2: Saturday, May 22, 6 pm, Building 23, Room 014

Final Exam: Monday, June 14, 7:30 am, Building 22, Room 134

Sample Exams

Exam 1 - Fall 2007

Exam 1 Solution - Fall 2007

Exam-2 - Fall 2007

Exam 2 Solution - Fall 2007

Instruction Sheet 2

Final Exam - Fall 2007

Final Exam Solution - Fall 2007


Lab work: 15%

Homeworks and Quizzes: 10%

Programming Assignments: 10%

Project: 15%

Midterm Exam I: 15%

Midterm Exam II: 15%

Final Exam: 20%


Course Topics



Course Topics


1, 2

Introduction to computer architecture, ISA versus organization, high-level, assembly, and machine languages, components of a computer system, processor datapath, control, memory hierarchy, disk storage, technology improvements, chip manufacturing process, programmer view of a computer system.

Chapter 1


Instruction set design, RISC design principles, MIPS registers, instruction formats, arithmetic instructions, immediate operands, bit manipulation, load and store instructions, byte ordering, addressing modes, flow control instructions, pseudo-instructions,  MIPS register conventions.

Sections 2.1 – 2.9

Sections 2.13, 2.15 – 2.18

Sections 3.2 – 3.3


MIPS assembly language programming, tools, program template, directives, text, data, and stack segments, defining data, arrays, and strings, array indexing and traversal, translating expressions, if-else statements, loops, indirect jump, console input and output

Appendix A


Runtime stack and its applications, defining procedures, procedure calls and return address, nested procedure calls, passing arguments in registers and on the stack, stack frames, value and reference parameters, saving and restoring registers, local variables on the stack


6 , 7

Integer multiplication, integer division, floating point representation, IEEE 754 standard, normalized and de-normalized numbers, zero, infinity, NaN, FP comparison, FP addition, FP multiplication, rounding and accurate arithmetic, FP instructions in MIPS.

Sections 3.2 – 3.3

Sections 3.4 – 3.6

Sections 3.8 – 3.9


CPU performance and metrics, CPI, performance equation, MIPS as a metric, Amdahl’s law, benchmarks and performance of recent Intel processors.

Chapter 4

9 , 10

Designing a processor, register transfer logic, datapath components, clocking methodology, single-cycle datapath, main control signals, ALU control, single-cycle delay, multi-cycle instruction execution, multi-cycle implementation, CPI in a multi-cycle CPU.

Sections 5.1 – 5.5


Pipelining versus serial execution, MIPS 5-stage pipeline, pipelined datapath, pipelined control, pipeline performance.

Sections 6.1 – 6.3


Pipeline hazards, structural hazards, data hazards, stalling pipeline, forwarding, load delay, compiler scheduling, hazard detection, stall and forwarding unit, control hazards, branch delay, dynamic branch prediction, branch target and prediction buffer.  

Sections 6.4 – 6.6

13 , 14

Cache memory design, locality of reference, memory hierarchy, DRAM and SRAM, direct-mapped, fully-associative, and set-associative caches, handling cache miss, write policy, write buffer, replacement policy, cache performance, CPI with memory stall cycles, AMAT, two-level caches and their performance, main memory organization and performance.

Sections 7.1 – 7.3

Sections 7.5 – 7.6


  Last Updated: Saturday September 01, 2012, by Dr. Muhamed Mudawar