COE 202 & EE 200 - Digital Logic Design Term 081 - Fall 2008 |
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Office: Building 22, Room 328, Phone: 4642 Syllabus | Lectures | Lessons | Assignments | Tools Announcements Final Exam: Tuesday, February 3 at 7 PM, Building 59, Room 1009 Major Exam 2: Monday, January 12 at 7 PM, Building 24, Room 141 Quiz 2 on Latches and Flip Flops - Saturday, January 10 Major Exam 1: Monday, November 24, 7 PM, Building 24, Room 120 Quiz 1 on Number Systems - Wednesday October 22 Assistant Jamil Mohamed Hamodi Email: g200604620@kfupm.edu.sa Any question related to grading should be directed to the teaching assistant Textbook M. Morris Mano and Charles Kime, Logic and Computer Design Fundamentals, Third Edition, Prentice Hall, 2004, ISBN 0-13-140539-X. Catalog Description Introduction to information representation and number systems. Boolean algebra and switching theory. Manipulation and minimization of completely and incompletely specified Boolean functions. Physical properties of gates: fan-in, fan-out, propagation delay, timing diagrams, and tri-state drivers. Combinational circuit analysis and design, multiplexers, decoders, comparators, and adders. Sequential circuit analysis and design, basic flip-flops, clocking and timing diagrams. Registers, counters, RAMs, ROMs, PLAs, PLDs, and FPGAs. Prerequisite: PHYS 102. Course Learning Outcomes
Academic Honesty View important information on academic honesty Exam Schedule Exam 1: Monday, November 24, at 7 PM, Building 24, Room 120 Exam 2: Monday, January 12, at 7 PM, Building 24, Room 141 Final Exam: Tuesday, February 3 at 7 PM, Building 59, Room 1009 Grading Assignments & Quizzes: 15% Project: 10% Major Exam I: 20% Major Exam II: 25% Final Exam: 30%
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Last Updated: Saturday October 03, 2009, by Dr. Muhamed Mudawar |