COE 202 Course CD

Digital Logic Design

mudawar@kfupm.edu.sa

Office: Building 22, Room 328, Phone: 4642

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 Unit I - Number System and Codes PDF Online 1 Introduction. Information Processing, and representation. Digital vs Analog quantities. 2 Number Systems. Binary, Octal and Hexadecimal #’s 3 Number System Arithmetic. Binary arithmetic (Addition, Subtraction & Multiplication). Arithmetic in other systems. 4 Number base conversion (Dec to Bin, Oct, and Hex, General). Conversion (Binary, Octal, Hexadecimal) 5 Binary Storage & Registers. Signed Binary Number representation, Signed Magnitude, R’s &(R-1)’s Complement 6 Signed Binary Addition and Subtraction. R’s Complement. Signed Binary Addition and Subtraction. (R-1)’s Complement 7 Codes.  BCD, Excess-3, Parity Bits, ASCII & Uni-Codes

 Unit II - Binary Logic & Gates PDF Online 1 Binary logic and gates, Boolean Algebra, Basic identities of Boolean algebra. Algebraic manipulation, Complement of a function. 2 Canonical and Standard forms, Minterms and Maxterms, Sum of products and Products of Sums. 3 Physical properties of gates: fan-in, fan-out, propagation delay. Timing diagrams. Tri-state drivers. 4 Map method of simplification: Two-, Three-, and Four-variable K-Map. 5 Map manipulation: Essential prime implicants, Non-essential prime implicants, Simplification procedure, POS simplification, Don’t care conditions and simplification, Five, and Six-variable K-Map. 6 Universal gates; NAND, NOR gates: 2-level implementation. Multilevel Circuits. 7 Exclusive-OR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation and checking.

 Unit III - Combinational Logic PDF Online 1 Combinational Logic, Design Procedure & Examples. 2 Half and Full Adders, Half and Full Subtractor, Ripple Carry Adder design and delay analysis 3 Carry Look-Ahead Adder, Binary Adder-Subtractor. BCD Adder, Binary Multiplier 4 MSI parts. Decoders, Decoder expansion,  combinational logic implementation using decoders, Encoders & Priority Encoders 5 Multiplexers, Function Implementation using multiplexers, Demultiplexers 6 Magnitude Comparator. 7 Examples of MSI designs

 Unit IV - Sequential Circuits PDF Online 1 Sequential Circuits: Latches, Clocked latches: SR , D, T and JK. Race problem in clocked JK-Latch. Function & Excitation Tables of clocked latches: SR, D, and JK. 2 Flip-Flops: Master-Slave, T-FF. Function & Excitation Tables of T-FF. Asynchronous/Direct Clear and Set Inputs. Setup, Hold 3 Sequential Circuit Design: Excitation Tables. Design procedure, State diagrams and state tables. 4 Sequential Circuit Analysis: Input equations, State table. 5 Mealy vs. Moore models of FSMs. Examples.

Unit V - Registers & Counters

PDF

Online

1

Registers, Registers with parallel load, Shift Registers. Bi-directional shift register.

2

#### Synchronous Binary Counters: Up-Down Counters.

3

Counters with Parallel  load, enable, synchronous clear and asynchronous clear. Use of available counters to build counters of different count.

4

Other counters: Ripple Counter, Arbitrary Count Sequence.

 Unit VI - Memory & PLDs PDF Online 1 Memory devices: RAMs & ROMs. Combinational Circuit Implementation with ROM 2 Programmable Logic Devices: PLAs, PALs, FPGA’a

Last Updated: September 2008, by Dr. Muhamed Mudawar