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Research Projects and Grants |
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Homepage | Schedule | Teaching | Publications |
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A Hybrid SW/HW Approach to Architectural Modeling and Simulation of Many Core CMPs NSTIP Project: 2013- 2015 Total Budget Allocation: SAR 1,044,500 The objective of this project is to develop a
framework that includes a software functional simulator and accurate
hardware timing simulator of the cache memory hirearchy and
interconnection network. Multicore Processor Prototyping NSTIP Project: 2009 - 2011 Total Budget Allocation: SAR 983,000 The major outcome of this project is a prototype multicore processor implemented on high-density FPGA chips. We will implement simple pipelined cores. Our projection is that we can have only one core per FPGA chip. Each core will include an instruction-execution pipeline with a register file, ALU, FPU (for executing floating-point instructions), a thread-fetch unit for fetching and scheduling threads, an instruction cache, a local data memory (or data cache), and a network interface unit (for communication with other cores and access to memory and I/O). Multiple FPGA chips will be used to build a large prototype. Our goal is to produce a quad-core prototype using four FPGA chips. We will also attempt to build a larger prototype with a larger number of cores if we have the resources.
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Multicore Vector Processor Design and Simulation KFUPM Internal Project: 2008 - 2010 Total Budget Allocation: SAR 219,800
Exploring the idea
of full vector support in a multicore architecture. Current multimedia
or streaming instructions cannot take advantage of the increasing number
of cores in a chip. Full vector support enables vector instructions
issued by a single core to broadcast and execute in all cores, thus
exposing and scaling data-level parallelism. The challenge is to have
full vector support at the micro-architecture level with minimal
extension to current multi-core designs. Part of this study is to
examine the effects of the vector support on the chip-interconnect and
the cache memory subsystem. |
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Parallel Primary Caches for Instruction and Data (2003 - 2005) Studied the effect of having parallel primary caches for
instructions and data to improve the bandwidth and capacity of primary
caches. |
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Multiway Channels for High Speed Interconnection Networks (1999 - 2003)
My contribution to this field is the
development of the new concept of multiway channel. A
prototype router chip was designed in VHDL. A simulation program was also developed to
evaluate the performance of large-scale multi-dimensional mesh and torus
networks. The simulation program can simulate multiway channel networks
of various topologies, sizes, routing algorithms, traffic patterns,
message lengths, and buffering requirements in routers and nodes. It can
generate a variety of statistics for all nodes and channels in a
network. Many problems have been investigated. These include
deadlocks, broadcasting to a region of nodes, multicasting to an
arbitrary set of nodes, routing in the presence of faults, and the
design and implementation of a versatile and reliable router to
implement networks of various topologies. |
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SIMPL Parallel Programming Language (1997 - 1999) My contribution to this area is the development of the SIMPL programming language. SIMPL is a parallel programming language that supports functional- and data-parallelism. This language features threads and parameterized types. A lot of effort has been spent on the implementation of this language. A primitive compiler for a sequential subset of SIMPL has been developed.
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Last Updated: Wednesday March 08, 2023, by Dr. Muhamed Mudawar |