Catalog Description

Number systems. Boolean Algebra and Minimization of Boolean functions. Combinational circuit analysis and design: multiplexers, decoders, adders, and ALU. Sequential circuits analysis: flip-flops, registers. MIPS instruction set architecture. Assembly language: selection and repetition structures. Single-cycle and pipelined processor design. Memory hierarchy, ROM, RAM, and cache memories. Evaluation of processor and cache performances.

Prerequisite: PHYS 104

Not to be taken for credit with COE 301, Not open for COE students.

Course Objectives

• To offer students basic and intermediate levels of knowledge on digital logic, assembly language, and computer organization.

• To enable students to design and evaluate logic circuits, pipelined processors, and cache memories.

Course Learning Outcomes

• Design small and medium scale logic circuits.

• Describe the instruction set architecture of a processor, such as MIPS.

• Design and implement MIPS assembly-language programs.

• Design the datapath and control of a single cycle and basic pipelined processors.

• Describe the organization and operation of memory and caches.

• Analyze and evaluate the performance of processors and caches.