Text Book and references:
- Text Book: Computer Organization & Design -
The Hardware/Software Interface : David A. Patterson and John L.
Hennessy, Second Edition, Morgan Kaufmann, 2002, and references:
- Scalable Parallel Computing, K. Hawng and X. Zhiwei,
McGraw-Hill, 1998.
- Computer Architecture : Design and Performance, Barry Wilkinson,
Prentice-Hall, 2nd Edition 1996.
- Computer Organization and Architecture : Designing for
Performance, William Stallings, Prentice Hall, Fourth Edition,
2001.
- Attendance: attendance is required by all students.
Excuse for official authorized must be presented to the instructor
no later than one week following the absence. unexcused absences
may lead to a ``DEN'' grade.
Course Objectives:
(1) To understand the basics of memory management,
(2) To learn the new trends in computer architecture,
(3) To study the design of pipelined processors,
(4) To comprehend the basic parallel architectures and interconnection
networks.
Catalog Description
Memory management and cache memory. Integer and floating point
arithmetic. Instruction and arithmetic pipelining, superscalar
architecture. Reduced Instruction Set Computers. Parallel
architectures and interconnection networks.
Prerequisite: COE 205.
COURSE TOPICS
- Introduction and Performance (1.5 weeks)
Introduction to computer Architecture (Sections 1.1 – 1.3), computer
technology (Sections 1.4 – 1.5). CPU Performance and Metrics
(Sections 2.1 – 2.3, evaluating performance and benchmarks (Sections
2.4 – 2.8).
- Computer Arithmetic. (2 weeks)
Signed and Unsigned Numbers (Sections 4.1 and 4.2), addition and
subtraction (Section 4.3), logical operations (Section 4.4),
constructing ALU (Section 4.5), multiplication and division
(Sections 4.6 and 4.7), floating point representation (Section 4.8),
and brief discussion on floating point in PowerPC and 80x86 (Section
4.9).
- Instructions: the language of the machine. (1 week)
Introduction and operations of the computer hardware and its
operands (Section 3.1 – 3.3), instruction Representation (Section
3.4), and making decisions, supporting procedure, addressing Modes
(Sections 3.5 – 3.8), and Brief overview of MIPS instruction set
(Section 4.11).
- Datapath and Control (2 weeks)
Single-cycle datapath (Sections 5.1 – 5.2), implementation datapath
(Section 5.3), and multi-cycle implementation (Section 5.4).
- Enhancing performance with pipelining (3 weeks)
Pipelined datapath (Sections 6.1 – 6.2), pipelined control (Section
6.3), data hazards and forwarding (Section 6.4), data hazards and
stalls (Section 6.5), branch hazards (Section 6.6), exceptions
(Section 6.7), and superscalar and dynamic pipelining (Section 6.8 –
6.9).
- Memory System Design (3 weeks)
Introduction and basics of caches (Sections 7.1 - 7.2), measuring
and improving cache performance (Section 7.3), virtual memory and
memory hierarchy (Sections 7.4 - 7.5), examples of memory
hierarchies (Section 7.6), and performance and trends (Section 7.7 -
7.8).
- I/O and Buses (1 week)
Introduction and I/O performance measure (Section 8.1), types and
characteristics of I/O (Section 8.3), and connecting I/O devices to
processor and memory using buses, (Section 8.4)
- Multiprocessors (1.5 weeks)
Introduction and programming multiprocessors (Sections 9.1 - 9.2),
and multiprocessors connected by a single bus and by a network
(Sections 9.3 - 9.4).
Computer Usage: Programming assignments may be required to
simulate various components of a computer like a pipeline, cache
memory, or a multiprocessor.
Working Groups:
The instructor encourages the students to work in groups for
reviewing the class lectures, preparation for exams, and discussion
(only) of homework problems. Participants receive bonus grades for
such activities. The organization of these groups is as follows. Any
student with a GPA above 3.0 can be considered as a class leader.
Each class leader is encouraged to create a Working Group of 3
or 4 students to review the course material of COE 308. A Bonus will
be given to all members of a Working Group for each meeting of the
group. Students with a GPA above 3.0 wishing to participate in this
activity are pleased to give their name and ID to the instructor.
Students wishing to participate as group members may ask the
instructor about the class leaders and their groups. The class
leader has the responsibility of providing the instructor the list
of students who attended a meeting. This list should include the
students name, date of meeting, and signatures. Any student can
attend the lecture review meetings with any of the Class Leaders.
POSSIBLE COURSE PROJECTS
- Study of Benchmarks programs used for Desktop computers.
The student will prepare for a refined presentation and a report
within six weeks. The suggested plan is: (1) determine
representative benchmarks most commonly used for Desktop computers,
(2) classify the benchmarks depending on their objectives such as
benchmarking the CPU, the display system, the hard disk, and the
NIC/Network, (3) acquire benchmarks as stated in (2), run them
during your presentation, comments on the results, and provide a
copy of those benchmarks to the students.
- Study of the SPIM processor simulator
The students will prepare for a refined presentation and a report
within six weeks. Steps are the following. First, take a code like
ADI benchmark, write it in assembly, generate its code in SPIM, and
collect its simulation and performance. Second try to restructure
the assembly code to improve performance. Third run the simulation
during your presentation, comments on the results, and provide
information on your project to other students.
- Free topics proposed by the students.