COE 501: Computer Architecture

Course Description:

Hardware and software approaches to ILP, dynamic, speculative, VLIW, and superscalar execution models. Examples and case studies. Dynamic branch prediction techniques. Memory hierarchy, cache and virtual memory, cache coherence, memory system performance. Parallel architectures models, coherence protocols, and interconnection networks. The students are expected to carry out research projects in related field of studies

Course Modules and Topcis:

1. Defining computer architecture, classes of computers, technology trends, power in integrated circuits, cost, performance metrics, Amdahl’s law, and benchmarks.
2. Instruction set architectures, simple pipelined processors, structural, data, control hazards, forwarding, dealing with exceptions and interrupts.
3. Memory hierarchy design, DRAM, cache organization, multi-level caches, cache optimizations, virtual memory, cache performance.
4. Instruction-Level Parallelism, data and control dependences, loop unrolling and compiler scheduling, branch prediction, dynamic scheduling, multiple-issue, speculation, out-of-order execution, precise exceptions, VLIW approach, limitations of ILP.
5. Data-level parallelism, Vector architecture, vector length, vector performance, SIMD instructions for multimedia, Graphics Processing Units (GPU) architectures, memory access, detecting and enhancing loop-level parallelism.
6. Thread-level parallelism, multi-threaded cores, multiprocessor architectures, memory models, cache coherence, and synchronization.