Background
	Introduction - An overview of the bus
	The S-100
	S-100 / IEEE 696
	ISA
	MCA
	EISA
	MCA Vs EISA
	Local Bus
	VL-Bus
	PCI
	VL Vs PCI bus
	Peripheral buses
	SCSI
	IDE
	SCSI Vs EIDE
	Conclusions

Backplane bus systems typically consist of a series of circuit boards mounted perpendicularly onto a motherboard via a series of slot connectors. This design allows for the exchange of bus devices and provides great flexibility in the range of devices a system can support (provided these devices adhere to the specific standard). Devices operating on a bus can be divided into two categories, bus masters and bus slaves. Bus masters are devices capable of initiating any bus cycle (memory read/write, port addressing, etc.) and bus slaves are devices which are not capable of initiating a bus cycle but merely responding to it. A third possible category are intelligent slaves which have their own intelligent controlling devices but do not assert control over the bus. A minimal bus has to feature three types of lines,

	Control lines
	Address lines
	Data lines

The control lines are responsible for passing control signals across the bus which instruct the devices when to read / write data. The address lines provide the memory or I/O device addresses detailing what exact locations data is to be read from / written to and the data lines provide a channel along which the actual data is transferred.

Another important aspect of buses is their dependence on related hardware. Some buses, for instance, are processor independent and can thus accommodate any of a range of microprocessors while other bus systems are designed around specific microprocessors or families or related microprocessors.

To illustrate typical bus operation, a generic PC-type bus consisting of a minimal series of lines (address, data and control/strobe lines) will be used. This illustration uses Programmed I/O to illustrate a typical bus operation since PIO tends to be quite straightforward. The control lines are used to synchronise data transfer by providing a series of pulses. Two possible schemes of control involve providing separate READ and WRITE control lines or a STROBE synchronising line and a READ/WRITE line with one state e.g. high denoting a read and the other denoting a write e.g. low. The PC bus tends to use separate READ and WRITE control lines (in fact 2 such lines for memory access and 2 additional lines for I/O access) so that scheme is adopted for the example - The CPU is sending data to a peripheral attached to the bus. The CPU asserts a strobe on the I/O write line. This pulse indicates that the preceding address on the address line is good and the addressed peripheral begins reading data from the data bus. The data write proceeds until such time as the strobe changes it level, this signals the end of the I/O write and data ceases to be read by the peripheral after a short period of time. There are other control signals involved on real bus systems but example above illustrates the minimum signals used on a system bus.

The S-100

Dimensions	134mm x 254 mm
Connector	100 pin edge type (50 on each side of the board, 3.17mm apart)
Voltage Supply	Unregulated +8V,+16V

In its time, the original S-100 bus was very popular with a large range of peripheral boards being available for it including memory boards, serial and parallel interface boards, floppy disk controller boards, video boards, music synthesiser boards and speech recognition boards.

As noted in the above table , the voltage supply on the S-100 bus was unregulated, this had both advantages and disadvantages. It made for a simpler power distribution system on the bus and a reduction in electrical interference between modules. On the other hand, this power distribution strategy required that every board have its own regulator which increases the cost of individual boards. A single, good regulator on the bus would have eliminated at least some board reliability problems. The actual location of the power pins (1, 2, 51, 52) was also questionable with any misalignment of cards leading to the possibility of serious electrical damage to the board components. This could have been prevented either by locating the pins such that no power flows if the board is misaligned or by locating the power lines between grounding lines.

The position of the clock lines in the original S-100 was also potentially problematic with the PHASE 2 CLOCK (2), PHASE 1 CLOCK (1) and 2 MHz clock signals being located near to 9 other control signals. The clock signals tend to occur continuously and have sharp rise and fall times. Unless they are shielded, they can become coupled to the adjacent lines.

The S-100 provided 16 data lines, 16 address lines (providing an maximum addressable space of 64k), 3 power-supply, 8 interrupt and 39 control lines. It actually provided many more control lines than were necessary. The 16 lines of the data bus provided 2 groups of unidirectional 8 bit lines (with one set providing data input and the other providing data output). This configuration was used as opposed to a bi-directional 8-bit group of lines, neither has any great advantage over the other particularly when a lot of S-100 devices actually recombined the signals on the boards.

Not all of the S-100 lines were clearly defined and since the S-100 could be used with a variety of processors including the Intel 8080, Zilog Z-80 and Motorola 6500 and 6800 microprocessors some lines were only generated by certain microprocessors. Also, the level of standardisation in the peripheral manufacturing industry was such that there was no specific agreement on what pins were for what. Most of the few hundred boards probably worked with most implementations of the S-100 but there was definitely some instances of conflict due to this lack of standardisation. In a nutshell, the S-100 bus became popular as manufacturers began to produce compatible boards in recognition of the popularity of the Altair. This, in turn, encouraged the makers of other microcomputers to incorporate the S-100 bus into their systems. A company called Cromemco actually coined the title S-100 (derived from 'Standard 100 bus') to give a common name to what

many manufacturers were claiming to be their own bus design.

S-100 / IEEE 696

A working party set up by the IEEE in 1983 forced a redesign and enhancement of the S-100 bus design. This was actually the first time the S-100 bus was formally specified. As well as ironing out ambiguities, the standard proposed a number of enhancements,

	An additional 8 address lines, giving a total of 24 (capable of addressing up to 16MB)
	Support for 16-bit microprocessors by way of a 16-bit data bus was added (the original pair of 8-bit unidirectional data bus lines could be combined to form a bi-directional 16-bit data bus). This extension was implemented with the addition of 2 new signals, sixteen request (SXTRQ, line 58) and sixteen acknowledge (SIXTN, line 60).
	3 ground lines were added at lines 20, 53 and 70 to provide more signal grounds
	Line 12 was standardised for the Non-maskable Interrupt (NMI) signal and 8 vectored interrupt signals are allocated such that an interrupt controller can be used by devices on the bus.

Other improvements to the original bus included the precise specification of all 100 lines, except 3 lines designated NDEFs (21, 65, 66) and 4 lines designated RFUs (27, 28, 69, 71) - reserved for future use. The RFUs may not be used by board makers but the NDEFs may be used as a manufacturer wishes provided that their logical function is clearly specified. The data rate of any signal on the bus was tied down to 6 MHz although in actual fact, boards capable of running at speeds of up to 10Mhz were common.

The S-100/696 bus can support 1 permanent bus master and up to 16 temporary bus masters, 4 DMA lines were designated for providing access to the temporary bus masters. Priority is dependent on the particular DMA line being accessed. In a step toward processor independence, some 8080-derived signals were deleted from the new standard such as, the interrupt enable signal (PINTE) which signalled the state of the interrupt enable flip-flop; the Wait command/control signal which when high acknowledges that the processor is in wait state (PWAIT); the Stack-status (SSTACK) output signal which, when high indicates that the address bus holds the pushdown stack address.

Even this rudimentary set of rules made a relatively large impact on the status of the S-100. It was future-proofed in a number of ways,

	It now had support for 16-bit microprocessors
	Due to the elimination of the 8080-specific signals, the S-100/696 fully supported a range of other microprocessors and was relatively manufacturer independent.
	The maximum addressable space of the bus had increased dramatically.
	Signal timings were clearly specified and the bus loading and termination impedances were clearly specified eliminating many of the early compatibility problems which were caused by signal reflection and crosstalk.

The S-100 was thus given a new lease of life with this standard and although there were technically superior buses in existence at the time, the S-100 found application in areas as diverse as small industrial control applications to multi-user electronic office systems running proprietary database and word-processing software. The two main reasons for its popularity were its price and the large number of manufacturers that supported it. Also, as manufacturers produce more and more boards to a certain bus specification, they tend to get better at using that bus and gain experience of its quirks, thus any manufacturer is understandably slow to migrate to other technology unless there is significant market demand coupled with sound technical reason for doing so.

ISA

The 62 pin XT bus did not support external bus masters with the only devices that could assert control over the bus being the CPU or the DMA controller on the motherboard. The key features of the XT bus are summarised below,

	20 address lines (A0-A19)
	8 data lines (bi-directional)
	Maximum data transfer rate of 1.2MB/s
	6 interrupt request lines (IRQ2-IRQ7)
	3 DMA lines
	4.77 MHz bus clock speed

The original XT bus was characterised by the simplicity of its design. It didn't provide any particularly innovative features and in a lot of respects it was limited by this simplicity (e.g. very limited number of Interrupt and DMA channels; limited maximum addressable space; narrow 8-bit data path and lack of bus master support), however it was well suited to the XT and performed quite well with the 8-bit 8088 processor around which the XT was built.

An enhanced version of the XT bus was designed for use in the IBM-AT ('Advanced Technology') which was introduced in 1984. Importantly, while this bus provided significant enhancements to the original XT bus architecture, it retained backward compatibility with the original XT bus allowing old cards to be used in ATs using the new bus which was retrospectively described as ISA (Industry Standard Architecture). The major improvements to the XT bus that led to ISA are described below, most of these were implemented using an optional, additional connector (thus facilitating backwards compatibility).

	A 16-bit data bus was implemented with the addition of 8 extra data lines.
	Maximum Addressable space was increased to 16MB with an additional 4 address lines (to give a total of 24).
	5 additional edge-triggered IRQ lines were added.
	Partial support for multiple bus masters was provided with the introduction of the signal.
	Maximum bandwidth of 5.3 MB/s
	8 MHz bus clock speed.

The bus mastering was not a complete or perfect implementation due to certain limitations such as a request by a Bus master for 'Bus hand-off' requiring several cycles for completion and the master having to relinquish the bus periodically to allow memory refresh (or do the refresh itself). It is important to note that IBM made an effort to ensure backwards compatibility with the XT-bus. As mentioned, most of the new features were implemented by adding on another connector to the bus which allowed extra features to be added without disrupting existing (XT) bus functions. The AT was built around the Intel 80286 which ran significantly faster than the original 8088 so a wait-state generator was added to lengthen the bus cycle. A bypass was provided via one unused line (pin 88) on the original bus (recalling that the XT bus used a 62 pin connector but only had 53 signal lines and 8 power lines). This pin became the zero wait state line (). When this line is being pulled low, some or all of the wait states generated by the AT motherboard are removed. By putting this signal on the 62-pin connector, IBM allowed manufacturers to make fast new 8-bit boards as well as fast 16-bit boards.

The new connector added 4 new address lines (A20-A23), plus copies of three lower address lines (LA17-LA19). This duplication was necessary because the address lines on the XT bus were latched (the address signals were tied to flip-flops which maintained the address lines logic level until explicitly set to a different value) and this latching process caused propagation delays that would slow down peripheral boards. By providing a duplicate set of these address lines, the AT-bus allowed 16-bit boards to find out early in the cycle if they were being addressed which allowed 16-bit cards to signal the bus that they could accept a 16-bit cycle. This key feature of the AT buses backward compatibility meant that if the 80286 attempted to perform 16-bit access to a board, it would only do so if the correct signals were asserted by the addressed peripheral, otherwise special hardware on the motherboard takes over and causes two 8-bit cycles to be performed. Unfortunately, due to there being only 7 unlatched address lines as detailed above, this signal could only instruct the board as to which 128K region of memory was being addressed, so a lot of memory boards that didn't use a full 128K block of real-mode address space could not activate the signal and thus were prevented from using 16-bit transfers, in reality this included a lot of EMS boards and memory-mapped peripherals.

It is worth noting at this stage that the timings of the PC and AT backplanes weren't formally specified by IBM at the time (clone-makers finally defined a pseudo-standard for timings when developing the EISA bus).

There is no doubt that the ISA bus was not technically exceptional by today's standards, however, it exceeded the requirements of most users in 1984 and IBM's dominance of the mass computer market with the AT led to mass adoption of the ISA bus by both peripheral board manufacturers and clone PC makers. This popularity is attested by the continued inclusion of ISA slots in most modern PCs (albeit in coexistence with faster local bus technologies). The proliferation of many reliable 16-bit ISA bus cards for a variety of tasks that do not require faster transfer speeds or wider data paths has led to its continued use in PCs for tasks such as networking (Ethernet 3Com etherlink III and Novell NE2000 ISA cards account for a large section of the LAN market). Single user machines also typically provide services such as sound-cards and hard-disk controllers through the ISA bus. Obviously, its popularity and relative simplicity made it a good choice for both board and PC manufacturers and it remains to suitable many roles.

MCA

MCA's key features are as follows,

	8/16/32 bit data transfer path
	20 MB/s maximum bandwidth
	Multiple bus master support
	11 Level-triggered interrupts as opposed to the ISA style edge-triggered interrupts (Level triggered interrupts allow sharing of interrupt lines thus eliminating one of the problems plaguing the original PC - a shortage of interrupt request lines).
	24 or 32 address lines (providing up to 4GB of addressable memory space).
	Automatic card configuration (rather than having hard-wired I/O port addresses, the CPU assigns an address at system start-up based on information from ROM on the cards).
	Asynchronous Data Protocol

Although MCA was technically capable, IBM's strong-arm tactics and the price tag of MCA cards resulted in IBM only slowly developing a market for this bus system. People who bought into MCA based systems were typically companies who were 'buying IBM', rather than buying MCA. IBM also provided an extension to the standard MCA slot by way of a video extension connector which was designed to speed up the video subsystem. The connector utilises video circuitry built onto MCA motherboards and allows added on boards to coexist with it and utilise its features. This supposedly provided a basic video system which could be relied on regardless of what add-on video card was present but in theory, the video extension was as proprietary as the bus system that spawned it and it never featured prominently in the video scene. In the two years following the introduction of MCA, only a few of the large clone manufacturers released MCA based machines, Apricot and Olivetti were two of the main supporters of IBM's new bus technology (and even Olivetti turned out to be burning both ends of the candle, playing an active role in the development of a competing bus standard, EISA). In September 1988, a competing bus technology was introduced by Compaq, dubbed EISA for Extended Industry Standard Architecture.

EISA

This architecture was the clone-makers response to IBM's proprietary, licensed MCA. Compaq, back by the 'Gang of Nine' - Wyse, AST Research, Tandy, Compaq, Hewlett-Packard, Zenith, Olivetti, NEC and Epson, announced a 32-bit bus extension to ISA which retained full compatibility with ISA. As with the XT to AT bus transition, extra functionality was provided by adding extra connectors to the AT bus. EISA features include,

	32-bit data transfers
	33 MB maximum bandwidth
	32-bit memory addressing, providing up to 4GB of addressable memory space (as with the ISA extension, the extra address lines were not latched providing for faster addressing).
	Multiple Bus masters
	Programmable level or edge-triggered interrupts (with a number of devices being able to share the same interrupt in the case of level-triggered interrupts).
	Automatic board configuration.

The new pins for the EISA bus were physically placed between the pins of the ISA bus. The EISA connector/socket was designed so that ISA cards inserted rest on a set of tabs which prevent ISA cards making any physical contact with EISA lines (which could possibly have occurred due to misalignment or mis-insertion of ISA cards otherwise). EISA cards carried a number of slots which allowed them to descend and make contact with the EISA lines.

The main signal lines added to the ISA standard to create the EISA standard are indicated below,

M-10	Distinguishes between an EISA memory cycle and an EISA I/O cycle
	Indicates the start of an EISA bus cycle
	Provides timing control within an EISA bus cycle
	Indicates that a master is capable of performing burst cycles
	Indicates that a slave is capable of accepting burst cycles.
EX32, EX16	Indicate that a slave is an EISA board and can support a 32-bit or 16-bit cycle respectively. If neither of these signals is asserted at the beginning of a cycle, the bus falls back to an ISA compatible mode for that cycle.
	Asserted by potential master number n to request the bus
	Indicates to master n that it has been granted the bus

An important feature of the EISA bus is that the host or any bus master can access any memory device or peripheral in the system, even if their bus widths differ. As indicated in the features list, for sheer speed EISA excelled providing a maximum 32-bit data transfer rate of 33 MB/s. While EISA supports level-triggered interrupt lines, it is important to note that older ISA cards cannot share interrupts even when plugged into an EISA connector, since they rely on older edge-triggering.

Bus master support in the EISA could be described as complete as opposed to that provided in the ISA bus. The memory refresh controller, the active DMA channel with the highest priority and peripherals vying for bus control compete for ownership of the bus by means of a three-way sharing scheme controlled by the EISA arbitration unit, the Integrated System Peripheral chip. The scheme ensures that no bus master is deprived access although it is possible for low-priority DMA channels to suffer. An additional watchdog on the system is provided by the Intel's Bus Master Interface Chip (BMIC) which ensures that no one master remains in control of the bus for too long. After a certain time period elapses, the master is removed from the bus and a non-maskable interrupt is generated by the CPU.

In conclusion, with EISA and 32-bit microprocessors (Intel's 80386 and 80486), the PC had grown up. It was no longer confined to personal computing and now provided the power to act as a workstation or a unix box running a few hundred terminals.

MCA Vs EISA

	MCA	EISA
Raw Bandwidth	20 MB/s	33 MB/s
Mode of communication	Asynchronous	Synchronous
Physical Dimensions of cards (length x width)	292.1mm x 88.2 mm	333.5 mm x 127.0 mm

One of the problems MCA would have given board-makers stemmed from its physical size. EISA cards provided nearly double the surface area afforded by MCA cards eliminating the need for expensive integration to build the same function in a smaller area. Power supply is also an important factor of comparison, an EISA adapter can use more than twice the power of an MCA adapter. This makes peripherals simpler and cheaper to implement in EISA.

EISA, in particular Intel's EISA chipset only supported the 80386 and 80486 chips in its own attempt to discourage the use of clone 286 processors in advanced machines while MCA featured on some 80286 based PS/2's as well as 80386 and 80486 machines. At the end of the day however, IBM remained the main supplier of both MCA cards and MCA-based PCs while EISA boxes could be bought safely in the knowledge that older ISA cards could be installed in them until faster cards became available. In general, EISA could have been said to have won the war since in instances where speed was an issue, EISA was the 32-bit bus of choice e.g. Graphics intensive systems. It's worth noting, however, that EISA never achieved the kind of market penetration envisaged by Compaq where it would replace ISA bus systems entirely, rather ISA continued to thrive in the low end of the market. By the time standard PCs were reaching the limits of ISA bus technology for tasks such as graphics, the local bus was beginning to show up effectively allowing standard PCs to bypass EISA technology.

Local Bus

The Local bus architecture takes a slightly different approach to that used by System I/O buses such as ISA, MCA and EISA by taking cards off of the expansion bus and connecting them directly to the CPU or across a bridge (integrated circuits that serve as signal amplifiers and repeaters) to the CPU. This eliminates the bottleneck of data throughput which existed when everything sat on an 8MHz bus. While 8MHz was fast enough for some devices, the performance of peripherals such as video adapters and hard-disk controllers was suffering by the early nineties. The solution was to give speed and bandwidth critical devices better access to the CPU and memory while allowing slower and older peripherals to remain on the ISA expansion bus. This was implemented by placing the ISA bus controller itself onto the local bus thus bridging the divide between local bus and slow peripherals. This was important, as had been proved by previous efforts such as IBM with MCA which neglected backwards compatibility with subsequent consequences for its popularity. Thus, most local bus implementations officially supported the bridging of older buses via a buffering scheme of some type. The two main contenders for the local bus market were VL-bus and PCI. There also existed various non-standard local bus implementations and non-specified architectures. Its important to consider that the development of processor direct buses was motivated by two main factors,

The development of next-generation microprocessors i.e. Intel's 80486 which ran at speeds of up to 66MHz (on a clock doubled chip). These processors ended up waiting for input from slow buses with older PCs, effectively mitigating any additional performance afforded by these chips.

The development of advanced graphics adapters which supported more colours and higher resolutions (VGA and SVGA) and faster hard-disk controllers which had to transfer much more information than the monochrome and character-based adapters of previous generation PCs (the demand for these adapters in turn was linked to the introduction and proliferation of graphical user interfaces such as Windows and OS/2).

VL-Bus

The first standard for local buses introduced in August, 1992 was the VESA local bus (or VL-bus). VESA (Video Electronic Standards Association) represented a group of over 100 companies who came up with a specification for a local bus implementation. The key features of VL-bus are summarised below,

	The Bus supports 386SX, 386DX and 486-type host CPUs. It is designed for use with single processor systems (the nature of VL-bus implementation wouldn't easily lend itself to working with multiple processor systems). Support for non x86 CPUs is also included in the VL bus specification by means of a bridge chip capable of abstracting the bus signals.
	There is a maximum of 3 bus masters supported on the VL bus system (this is in addition to the local bus controller), but it is possible to include a number of subsystems if additional masters need to be supported.
	Primarily developed to support high speed video controllers, although also expected to support other items such as hard-disk controllers.
	Bus speeds of up to 66MHz are supported but the electrical characteristics of the physical VL-bus connector limit the speed of devices operating across the connector to 50MHz (slotless devices such as integrated graphics devices would presumably not suffer from this limitation). In addition, clock doubled chips e.g. 486DX2-66 must halve their CPU clock before driving the VL-bus clock (this, in this instance, the bus speed would be 33MHz).
	Future compatibility for devices was included whereby all VESA-compatible devices would function on current and future VL-bus implementations without modification.
	The bi-directional data bus has a width of 32 bits but VL-bus also handles 16-bit transfers. The specification also reserves space on the board for a future 64-bit capable version.
	Full DMA support is provided with the bus devices needing to be full bus masters to take control, no DMA initiators are supported by the bus.
	Maximum theoretical bandwidth of 160 MB/s (this being on a 50MHz bus), with typical bandwidths of 107MB/s being achievable on 33MHz buses.
	Burst mode transfers are supported by VL-bus for 486 motherboards that are capable of burst transfer, with VL-bus using 5 identifier pins to identify the type and speed of the host CPU. The Burst Last (BLAST#) signal is used to activate burst capable systems. It is maintained low on non-capable systems.
	The bus sports a 58-pin MCA type connector. A maximum of 3 slots is supported (and this decreasing to 1 on certain 50MHz buses).
	VL-bus is physically in-line with the ISA or EISA connector, thus all (E)ISA signals are available to VL boards.
	Caching is supported for both CPU and motherboard caches.
	Power is provided in the form of 5 volt supply lines but devices that output 3.3 volt logic are also supported provided they can tolerate 5 volt input levels.

The VL bus was a long way from the decade old ISA bus, both in terms of its performance and its design. Not only was it fully specified but it was designed with the future in mind. The VL-bus 2.0 specification even outlined a 64-bit data bus standard. When it was introduced, VL-bus was the system of choice for premium graphics performance as was intended. Manufacturers had been slow to support any of the proprietary local buses due to fears of investing heavily in technologies that could become obsolete overnight. VL-bus provided a reliable platform on which manufacturers could base their more advanced graphics adapters.

One of the design intentions with VL-bus was to come up with a specification that allowed for the design of boards which used existing chipsets and very little glue logic chips which increase card costs. This was a bonus to manufacturers and users alike in that as well as offering high performance cards, they could offer them at a low price, lower in fact than similar EISA cards.

Clearly VL-bus was a winner, at least in the short-term for this is how many in the industry viewed it, particularly Intel who were working on their own local bus implementation, PCI. VESA proposed that VL and PCI could live in harmony with the bridging capabilities of VL allowing both buses to coexist in a system. Intel agreed that this was possible but posed the rather obvious question of why one would want both. Intel viewed the VL-bus as technology based on 11 year old PC architecture. It was essentially a quick fix in their view, a product of the compromise between different manufacturers. Another potential problem with VL-bus is that the bus is driven directly by the CPU and Intel discouraged the placing of cards directly on the CPU bus since the output signals of the 80x86 are not designed to drive the heavy loads usually associated with a bus and card structure. The VL-bus specification was designed to ensure that no damage was possible but the argument existed that a badly-designed card could damage a system.

PCI

In 1992, Intel announced its own local bus technology dubbed Peripheral Component Interface (PCI) to challenge VESA's VL-bus. Intel had designed PCI from the ground up rather than implementing it as an enhancement or quick fix to the bandwidth problems occurring in the PC. Intel claimed they had spent over 2000 hours in simulations of the PCI bus on sophisticated SPICE software which allowed them to analyse potential problems with the PCI signals and modify the basic design to smooth out these flaws. The PCI standard was turned over to the PCI Special Interest Group making it an open standard. One of PCI's features is that of not being quite as local to the CPU as VL-bus, instead it operates over a bridge to the CPU bus, this has the added advantage of making it totally processor independent with a bridge chipset abstracting the CPU signals. Nonetheless, PCI is a local bus implementation. Its key features are listed below,

	Synchronous 32-bit bus that carries both data and addresses.
	Capable of operation with 5 or 3.3 volt logic by means of separate keyed power supplies for both voltages.
	Bus speeds of up to 33MHz (with provision for a future version supporting speeds of 66MHz).
	Transfer rates as high as 132 MB/s using burst mode.
	Full multiple master capability e.g. several hard-disk controllers could operate simultaneously on the bus.
	Write-back and write-through caching supported.
	Automatic configuration of PCI add-in cards at power-up.
	The PCI specification allows for up to 8 functions on a single card (e.g. a combination of video, sound, etc.).
	PCI supports a maximum of 4 slots due to bus loading limitations but multiple PCI subsystems can be used with bridging.
	PCI devices are equipped with a latency timer which is used to define the maximum amount of time the device is allowed to use the bus.

The 66MHz bus speed has actually been implemented on some of Intel's newer PCI chipsets (e.g. Triton II) but as per the PCI 2.1 specification, the bus will only operate at 66MHz if all peripherals are operating at this rate, otherwise it reverts to 33MHz operation. As with VL-bus, the system I/O bus can be bridged to the PCI bus to include support for the older ISA and EISA card types. This technology has even been used to implement VL to PCI bridging schemes which provide both types of local bus on the same system.

The PCI bus defines three types of address space, the two usual ones of memory and I/O and an additional space for configuration information. Each PCI device is equipped with a 256-byte area, which includes details about the device and it's type i.e. network adapter, disk-controller, graphics adapter. At system start-up, this configuration area is scanned for each PCI device and each device is assigned a unique base address and interrupt number. PCI uses the one bus for both address and data signals by multiplexing them i.e. the same electrical conducting paths are used to carry both signals although not at the same time. An additional signal line indicates whether address or data information is on the bus. This multiplexing allows the PCI board to have a relatively small number of pin-outs, which decreases the size of the connector and also decreases the area of the motherboard used by the card.

PCI was obviously designed to be future-proof with features such as 66MHz bus speed and 64-bit bus widths being assessable when the need arises and the computer industry in general has endorsed the design by supporting it. Companies has varied as Apple and Digital have plans to or already include PCI in their machines. (Apples latest generation of Power Macintoshes use PCI instead of NuBus and DEC has gone so far as to implement built in PCI support to some of its RISC chips).

VL Vs PCI bus

The key features of SCSI are as follows,

	8-bit parallel I/O bus
	Each adapter can support up to 7 devices
	Various devices including cd-roms, tape drives, scanners and optical storage devices (including magneto-optical drives) are supported.
	Cable lengths of up to 6 meters are supported allowing devices to reside outside of the main computer case.
	Data transfer rates of up to 4MB/s are supported.
	Synchronous and asynchronous data transfer schemes are supported.
	Long cables require terminators to be placed on devices at the end of the SCSI daisy-chain.

SCSI-2 improved on the original standard in a number of areas, giving an improvement in flexibility and higher performance. The bus-width was increased to include 16 and 32 bit buses. With a maximum speed of 10MB/s on the 8-bit bus, speeds up to 40MB/s are supported on the 32-bit bus. The SCSI-2 specification allows any of the above combinations thus giving rise to a number of different subsets of SCSI-2,

Narrow SCSI	8-bit version of SCSI
Wide SCSI	16 and 32 bit versions of SCSI-2
Fast SCSI	SCSI-2 that supports 10MB/s speed

These implementations can be combined to give various different versions such as Fast-Wide SCSI for instance. A SCSI-3 specification is currently under development by ANSI, again including support for a faster bus. It will also implement longer cables, possibly of different types (e.g. copper, optical fibre, etc.). Support for a serial version of SCSI-3 is also being worked on.

IDE

Integrated Drive Electronics or IDE was developed by Western Digital and Compaq as a disk interface. It was derived from older disk interface controllers. It is not strictly speaking, a bus architecture (although some features of EIDE make it as nearly as much bus as SCSI is), but it serves as an interesting comparison to SCSI. The two features which made it the most popular disk interface in PCs are its ease of use and its price. It's key features are listed below,

	Transparent to applications software, IDE is defined in the PC BIOS and IDE interface.
	Supports two magnetic media drives (thus excluding devices such as cd-rom).
	As suggested by the name, all controller electronics are built into the drive.
	Data transfers of up to 4.1 MB/s are supported.
	40-pin connector interface.
	528MB disk capacity limit (this limitation is linked to the implementation of IDE through the BIOS).
	IDE interface can sit on either the system I/O bus such as ISA or on the local bus.

1994 saw the introduction of Enhanced IDE (EIDE) which upgraded the standard to allow IDE to be used with current technologies and to improve its speed performance. Improvements include,

	Increased data transfer rate of 10MB/s
	Drive capacities up to 8.4GB.
	Increased number of supported devices to 4 (with the addition of a second channel, up to two EIDE controllers can be used on a bus).
	Support for optical devices and cd-rom is included in the enhanced specification
	A maximum cable length of 18 inches is defined

SCSI Vs EIDE

Advances in bus design are intrinsically linked to two things,

	Improvements in overall computer performance (including microprocessors, graphics cards, etc.)
	Demand from users for higher performance machines due to advances in Operating Systems and interfaces.

References

	The S-100 & Other Micro buses, 2nd Ed., Elmer C. Poe and James C. Goodwin
	Upgrading and Repairing PCs, 3rd Ed., QUE
	The Art of Electronics, Horowitze and Hill
	"Fast Transit", Byte, October 1992, p122-136
	"Inside the PCI Local Bus", Byte, February 1994, p177-180
	"S100 in commerical applications", Micro & Microsyst, vol 10 no 2,March 86
	"Inside EISA", Byte November 1989, p417-425
	"System Bus or Bottleneck", Byte March 1992, p131-138
	"Back of the bus", Byte August 1994, p109-116
	VESA 2.0 VL-bus specification
	"The EISA Story", PC User, 10-23 May 1989
	The PCI faq
	Intel Support Web-site
	Bus Systems

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Copyright © 1997 by Stephen Mulcahy (stephen@skynet.ie )