A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design

Paper title

“A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design”

Authors: Sadiq M. Sait and Sanaullah Syed
Affiliation: College of Computer Sciences & Engineering, King Fahd University of Petroleum & Minerals, Dhahran, Saudi Arabia

Abstract:—Tabu Search based cell placement approaches for VLSI circuit design have shown excellent results when executed on a single processor. However, they require significant computation time. Of the various acceleration strategies attempted, parallelization has always exhibited the most potential. The parallel Tabu Search approach presented in this work can be classified as a synchronous master-slave p-control, RS and MPSS strategy. The approach is implemented on a dedicated Linux-based cluster of workstations, using MPI libraries for communication. Experimental results for ISCAS'89 benchmark circuits show excellent performance in terms of scalability & speed-up.