CS 282 (KAUST) - Spring 2010
Computer Architecture and Organization


Muhamed F. Mudawar


KAUST Office: Building 1, Room 4210, Office Hours: Tuesdays, 10:30 am - 12:30 pm

KFUPM Office: Building 22, Room 328, Phone: 03-8604642

Schedule and Office Hours

Syllabus | Lectures | Assignments | Tools and Simulators


Project Presentations: Tuesday May 18, 9 am - 2:30 pm, Lecture Hall 1

Midterm Exam: Tuesday April 20 at 12 - 3 PM, Room 2322 (Lecture Hall 1)

Project document updated on March 11 - Proposal due on March 23

Read Appendix A: Pipelining Basic and Intermediate Concepts

Read Chapter 1: Fundamentals of Computer Design, H&P textbook


Sharan Kalwani  sharan.kalwani@kaust.edu.sa

Building 14, Level 4, Room 10, Phone 808-1109

Ying Qian  ying.qian@kaust.edu.sa

Building 1, Level 0, Room 0125, Phone 808-0223

Dinesh Kaushik  dinesh.kaushik@kaust.edu.sa

Building 1, Level 0, Room 0117, Phone 808-0231

Questions related to assignments and grading should be directed to the teaching assistants. You may also seek the help of the teaching assistants on your projects.


John Hennessy and David Patterson, Computer Architecture: A Quantitative Approach, Fourth Edition, Morgan Kaufmann Publishers, 2007.

Catalog Description

Prerequisite: CS 209. Credits: (3-0-3)

Advanced topics in cache hierarchies, memory systems, storage and IO systems, interconnection networks and message-passing multiprocessor systems (clusters). Issues such as locality, coarse-grain parallelism, synchronization, overlapping communication with computation, hardware/software interfaces, performance/power trade-offs and reliability. Characteristics of modern processors that affect system architecture.

Exam Schedule

Midterm Exam: Tuesday April 20, 12 noon - 2:15 pm, Building 9, Room 3131


Assignments: 20%

Project: 50%

Midterm Exam: 30%

Course Topics



Course Topics


1, 2

Fundamentals of Computer Design

Classes of computers, instruction set architecture, technology trends, performance trends, power in integrated circuits, cost, dependability, computer performance, CPU time, CPI, MIPS, FLOPS, Amdahl's law, Benchmarks.

Chapter 1

3, 4

Pipelining: Basic Concepts

Classic five-stage pipeline for a RISC processor, structural hazards, data hazards and forwarding,  branch hazards, performance of a pipeline with stalls, pipeline implementation, dealing with exceptions, handling multicycle operations.

Appendix A

5 - 7

Instruction Level Parallelism and Advanced Pipelining

ILP concepts, data dependences and hazards, control dependences, loop unrolling and compiler scheduling, static and dynamic branch prediction, Tomasulo dynamic scheduling, hardware-based speculation, multiple-issue processor, VLIW approach, advanced pipelining and speculation, limits of ILP.

Chapters 2, 3

8 - 10

Memory Hierarchy Design

Typical memory hierarchy, cache memory concepts, cache organization, cache performance, reducing cache hit, misses, and miss penalty,  multi-level caches, advanced cache optimizations, memory technologies, virtual memory.

Chapter 5

Appendix C

11 - 13

Multiprocessors and Thread-Level Parallelism

Classification of parallel architectures, models for communication and memory architecture, symmetric shared memory, cache coherence, snooping protocols, distributed shared memory, directory-based coherence, synchronization, memory consistency.

Chapter 4


  Last Updated: Sunday May 09, 2010, by Dr. Muhamed Mudawar