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1. Abd-El-Barr,
M. H., M. Nadeem, and K. Al-Tawil, “A Heuristic-based Routing Algorithm for
Hypercube Multicomputer Networks”, Cluster Computing Journal, vol. 4, pp.
253-262, July 2001.
2. Abd-El-Barr,
M. H., K. Al-Tawil, and T. Al-Jarad, “RAZAN: A High Performance Switch
Architecture for ATM Networks", International Journal of Communication
Systems, vol. II, pp. 275-285, November 1998.
3. Abd-El-Barr,
M. H., G. Abdul-Hamid and M. Hasan, "On the Synthesis of MVL Functions
using Input and Output Assignments", IEE Proceedings Circuits and Systems,
vol. 145, no. 3, June 1998, pp. 207-212.
4. Y.
Wang, Abd-El-Barr, M. H., and C.
McCrosky, "An Algorithm for Symmetric OBDD Detection", IEEE
Transactions on Computers, vol. 46, no. 6, June 1997, pp. 731-733.
5. Al-Tawil,
K., Abd-El-Barr, M. H., and Ashraf, F., "A Survey and Comparison of
Fault-Tolerant Routing Techniques in Mesh Networks", IEEE Network,
March-April 1997, pp. 38-45.
6. D. Ekong,
H. Wood, and Abd-El-Barr, M. H., "Fault-Tolerant Neural Network with Concurrent
Error Detection and Correction Capability", Canadian Journal of Electrical
and Computer Engineering, vol. 22, no. 1, 1997, pp. 13-18.
7. J. Zhu,
Abd-El-Barr, M. H., and C. McCrosky,
"A New Theory for Testability-Preserving Optimization of Combinational
Circuits", VLSI Design International Journal, vol. 5, no. 1, 1996, pp.
59-75.
8. Wang, Y.
and Abd-El-Barr, M. H., "A New Algorithm for RNS Decoding", IEEE
Trans. on Circuits and Systems,
vol. 43, no. 12, December 1996, pp. 998-1001.
9. Abd-El-Barr,
M. H., and S. Ansari, "Statistical Analysis of Multiple Intermittent
Faults in Combinational Circuits", International Journal of Electronics,
vol. 80, no. 5, May 1996, pp. 647-660.
10. Abd-El-Barr,
M. H., and Hai, M. A., "Subcube Reliability of a Modular Fault Tolerant
Hypercube Architecture" Kuwait Journal of Science and Engineering, Vol. 2,
no. 1, 1996, pp. 7-25.
11. Abd-El-Barr,
M. H., McCrosky, C. D., and W. Li., "A Less Expensive Test Pattern
Generation Technique", Proc. IEE Pt. E, vol. 143, no. 1, January 1996, pp.
17-22.
12. Xu, Y.,
Abd-El-Barr, M. H., McCrosky, C., "Graph-Based Output Phase Assignment for
PLA Minimization", IEEE Trans. Computer-Aided Design (CAD) of Integrated
Circuits and Systems}, vol. 14, no. 5, May 1995, pp. 613-622.
13. Li, W.,
Abd-El-Barr, M. H., McCrosky, C., and Wei, D., "D-CPT: A Time/Space
Efficient Fault Simulator" International Journal of Electronics, vol. 76,
no. 4, April 1994, pp. 633-645.
14. Jain, A.
K., Bolton, R. J., and Abd-El-Barr, M. H. , "CMOS Multiple-Valued Logic
Design - Part I: Circuit Implementation", IEEE Trans. on Circuits and
Systems, vol. 40, no. 8, Aug. 1993, pp. 503-514.
15. Jain, A.
K., Bolton, R. J., and Abd-El-Barr, M. H., "CMOS Multiple-Valued Logic
Design - Part II: Function Realization", IEEE Trans. on Circuits and Systems,
vol. 40, no. 8, Aug. 1993, pp. 515-522.
16. Zhu, J. and
Abd-El-Barr, M. H., "On the optimization of MOS circuits", IEEE
Trans. on Circuits and Systems, vol. 40, no. 6, June 1993, pp. 412-422.
17. Zhu, J. and
Abd-El-Barr, M. H.,"
: A Totally Self-Checking Checker/Corrector with
Self-Exercising", International Journal of Electronics, vol. 74, no. 5,
May 1993, pp. 683-695.
18. Abd-El-Barr,
M. H., and H. Choy, "The Use of Simulated Annealing to Reduce 2-Bit
decoder PLAs", International Journal of Electronics. vol. 74, no. 3, March
1993, pp. 441-450.
19. Jain, A.,
Abd-El-Barr, M. H., and Bolton, R., "A New Structure for CMOS Realization
of MVL Functions", International Journal of Electronics, vol. 74, no 2,
Feb. 1993, pp. 251-263.
20. Abd-El-Barr,
M. H., "Programmable Synthesis of Multi-valued Multi-threshold Functions
for Implementation Using Charge-Coupled Devices", International Journal of
Electronics}, vol. 73, no. 2, 1992, pp. 345-370.
21. Abd-El-Barr,
M. H., "Systematic Realization of Binary and Multi-valued Functions Using
Charge-Coupled Devices Building Blocks", Proc. IEE-G, vol. 138, no. 6,
Dec. 1991, pp. 694-702.
22. Tandri, S.,
M. H. Abd-El-Barr, and C. McCrosky, "Integrated Specification, Simulation,
and Fabrication of Systolic/Wavefront Arrays", International Journal in
Computer Simulation, vol. 1, no. 3, pp. 273-290, 1991.
23. Abd-El-Barr,
M. H., Z. G. Vranesic, and S. G. Zaky, "Algorithmic Synthesis of MVL
Functions for CCD Implementation", IEEE Trans. Comput., vol. 40, no. 8,
pp. 977-986, August 1991.
24. Abd-El-Barr,
M. H., "A CMOS Quaternary Logic Encoder-Decoder Circuits",
International Journal of Electronics, vol. 71, no. 2, pp. 279-296, 1991.
25. Abd-El-Barr,
M. H., "Programmable Logic Array Structure for Realization of Multi-valued
Multi-threshold Functions Using Charge-Coupled Devices", International
Journal of Electronics, vol. 70, no. 4, pp. 765-783, 1991.
26. Abd-El-Barr,
M. H. and Z. G. Vranesic, "Cost Reduction in the CCD Realization of MVMT
Functions" IEEE Trans. Comput, vol. 39, no. 5, pp. 702-706, May 1990.
27. Abd-El-Barr,
M. H. and Z. G. Vranesic, "Charge-Coupled Device Implementation Of MVL
Systems", Proc. IEE-E, vol. 136, no. 4, pp. 306-315, July 1989.
28. Abd-El-Barr,
M. H. and Z. G. Vranesic, "The Incremental-Cost Approach for Synthesis of
CCD 4-valued Unary Functions", International Journal of Electronics, vol.
67, no. 5, pp. 735-748, 1989. (This paper won the Certificate for Best Paper
during the 18th ISMVL Symposium, in Spain, May 1988).
29. Abd-El-Barr,
M. H., Z. G. Vranesic and S. G. Zaky, "Synthesis of Multi-Valued
Multi-Threshold Logic Functions for CCD Implementation", IEEE Trans.
Computers, vol. C-35, no. 2, pp. 124-133, Feb. 1986.
30. M. R.
ElKaraksy, A. S. Noah and M. H. Abd-El-Barr, "Communication Channels
Microprocessor Based Interface For Bit oriented Line Protocols", Journal
of Engineering Sciences, vol. 5, no. 2, pp. 207-211, Nov. 1979.
Conference
papers
31. Abd-El-Barr,
M., Zakir, A., Sait, Sadiq, and Almulhem, A., “Iterative Heuristics in
Topological Optimization of Computer Networks Subject to Fault Tolerance and
Reliability”, Submitted, IEEE Infocom 2003 (IEEE Conference on Computer
Communications), to be held San Francisco, USA, March 30-April 3, 2003.
32. Abd-El-Barr,
M. and Zakir, “Enumerative Techniques in Topological Optimization of Computer
Networks Subject to Fault Tolerance and Reliability”, Submitted, IEEE Infocom
2003 (IEEE Conference on Computer Communications), to be held San Francisco,
USA, March 30-April 3, 2003.
33. Abd-El-Barr,
M. and Zakir, “The use of Enumerative Techniques in Topological Optimization of
Computer Networks Subject to Fault Tolerance and Reliability”, Accepted, 14th
IASTED International Conference on Papallel and Distributed Computing and
Systems (PDCS-2002), to be held Cambridge, USA, November 4-6, 2002.
34. Abd-El-Barr,
M. , Khan, Salman, and Baig, Zubair, “Performance Analysis of a Hybrid Scheme
for Tolerating Mobile Support Station Faiulres”, Proceedings International
Conference on Wireless Networks, Las Vages, USA, 2002.
35. Abd-El-Barr,
M. and Fadol, A., “A Self Organizing Neural Network using Cascaded Adaptive
Resonance Theory (CART)”, Accepted, Parallel and Distributed Computer Systems
(PDCS-2002) to be held Louisville, Kentucky, USA, September 19-21, 2002.
36. Abd-El-Barr,
M. and Sarif, Bambang, “Reliability and Yield Enhancement of Array Processors
(Part I): Hybrid Techniques”, Submitted, International Arab Conference on
Information Technology (ACIT-2002), to be held Doha, Qatar, December 16-19,
2002.
37. Abd-El-Barr,
M. and Sarif, Bambang, “Reliability and Yield Enhancement of Array Processors
(Part II): Local and Global Techniques”, Submitted, International Arab
Conference on Information Technology (ACIT-2002), to be held Doha, Qatar,
December 16-19, 2002.
38. Khan, S.
and Abd-EL-Barr, M., “On the use of Fuzzy Logic in a Hybrid Scheme for Tolerating Mobile
Support Station Failures”, 2002 IEEE International Conference on Fuzzy Systems
(Fuzzy-IEEE), May 12-17, 2002, Honolulu, HI, USA.
39. Abd-El-Barr, M. and Khan, Salman, “A
hybrid Scheme for Tolerating Mobile Suppport Station Faiulres”, Proceedings
ISCA Conference on Parallel and Distributed Computing, Dallas, USA, August
2001, pp. 436-441.
40. Khan, S.
and Abd-EL-Barr, M., “A Hybrid Fault Tolerant Mobile Communication Systems”,
IEEE Technical Exchange Meeting, Dhahran, Saudi Arabia, XXX
41. Abd-El-Barr,
M., C. Sundaram, and A. Almulhem, “VLSI Considerations in the Design of k-ary
n-cube Interconnection Networks”, IEEE International Symposium on Circuits and
Systems (ICSCAS), held May 6-9, 2001, Sydney, Australia, pp. 287-291.
42. Abd-El-Barr,
M. H. and Abdullah Al-Mutawa, “A New Improved Cost-table-based Technique for
Synthesis of 4-valued Unary Functions Implemented using Current-Mode CMOS
Circuits”, the 31st IEEE International Symposium on Multiple-valued
Logic (ISMVL-31), held May 22-24, 2001, Warsaw, Poland, pp. 200-206.
43. Abd-El-Barr,
M. and Salman, A., “A Hybrid Scheme for Tolerating Mobile Support Station
Failures”, the 4th International Conference on Parallel and
Distributed Systems, held 8-10 August, 2001, Dallas, Texas, USA, pp. 301-305.
44. Abd-El-Barr,
M. H. and Abdullah Al-Mutawa, “Cost-Analysis of 4-valued Unary Functions
Implemented using Current-Mode CMOS Circuits”, 30th IEEE
International Symposium on Multiple-valued Logic (ISMVL-30), held May 23-25,
2000, Portand, Oregon, USA, pp. 215-220.
45. Hasan Cam,
Abd-El-Barr, M. H., and S. Sait, "Design and Analysis of a
High-Performance Hardware Efficient Memory Allocation Technique",
Proceedings of the ICCD'99, held October 10-13, 1999, Austin, Texas, USA, pp.
274-276.
46. Abd-El-Barr,
M. H., and Z. Vranesic, "Design Issues in Field programmable Gate Arrays
(FPGAs)", Proceedings of the 11th International Conference on
Microelectronics (ICM), held November 22-24, 1999, Kuwait, pp. 169-172.
47. Abd-El-Barr,
M. H., V. Fortugno, and R. Bolton, "Design of a Four-Valued Current-Mode
VLSI CMOS Standard Cell Library", Proceedings of the 11th International Conference on
Microelectronics (ICM), held November 22-24, 1999, Kuwait, pp. 149-152.
48. Abd-El-Barr,
M. H., Yanging Xu, and Carl McCrosky, "Transistor Stuck-Open Fault
Detection in Multilevel CMOS Circuits", Proceedings of the 9th Great Lakes Symposium on VLSI, held
March 4-6, 1999, Ann Arbor, Michigan, USA, pp. 388-391.
49. Abd-El-Barr,
M. H., and Henry Fernandes, "Synthesis of MVL Decision Diagrams using
Current-Mode CMOS Circuits", Proceedings of the IEEE 29th International Symposium on
Multiple-Valued Logic (ISMVL-99), held May 20-22, 1999, Freiburg, Germany, pp.
160-165.
50. Abd-El-Barr, M. H., Maher El-Sherif, and
Mohammed Osman, "Fault Characterization and Testability Considerations in
MVL Circuits", Proceedings of the IEEE 29th International Symposium on
Multiple-Valued Logic (ISMVL-99), held May 20-22, 1999, Freiburg, Germany, pp.
262-267.
51. Abd-El-Barr,
M. H., and M. M. Abd-EL-Barr,
"A Frontier Algorithm for Optimization of Multiple-Valued
Functions", Proceedings of the IEEE 28th International Symposium on
Multiple-Valued Logic (ISMVL-98), held May 27-29, 1998, Fukuoka, Japan, pp.
245-249.
52. Abd-El-Barr, M. H., M. Hasan, and G.
Abdul-Hamid, "On the
Synthesis of MVL Functions using Input and Output Phase Assignments",
Proceedings of the IEEE 27th
International Symposium on Multiple-Valued Logic (ISMVL-97), May 28-30,
1997, Nova Scotia, Canada, pp. 253-258.
53. D. Ekong,
H. Wood, and Abd-El-Barr, M. H.,
"Fault-Tolerant Architecture for feedforward Artificial Neural
Networks", Proceedings of the IASTED International Conference on Parallel
and Distributed Computing and Systems, Oct. 16-19, 1996, Chicago, Illinois,
USA, pp. 223-225.
54. Khalid Al-Tawil, Feroze Daud, and
Abd-El-Barr, M. H., "A Modular Multiprocessor System Based on Hypercube
and Torus", 9th International Conference on Parallel and
Distributed Computing Systems (PDCS'96)", Sept. 25-27, 1996, Dijon,
France, pp. 324-329.
55. M. H. Abd-El-Barr, and Hasan, M. N.,
"New MVL-PLA Structures based on Current-mode CMOS Technology", IEEE
International Symposium on Multiple-Valued Logic (ISMVL-96), Spain, May 29-31
1996, pp. 98-103.
56. Abd-El-Barr, M. H., Daud, F., and
Al-Tawil, K., "A Hierarchical Fault-Tolerant Interconnection
Network", IEEE International Phoenix Conference (IPCCC'96), held March
1996, Phoenix, Arizona, USA, pp. 123-128.
57. Abd-El-Barr, M. H., Khalid Al-Tawil, and
Osama Abed, "Fault-Tolerance and Reliability Analysis of Multi-Stage Data
Manipulator Networks", 8th IEEE International Conference on Parallel and Distributed
Systems (PDCS-95), Sept. 20-23, 1995, Orlando, Florida, USA, pp. 275-280.
58. Abd-El-Barr, M. H., A. M. Abdul Hai, and
M. S. Benten, "The Subcube Reliability of a Fault-Tolerant Hypercube
Architecture", 8th
IEEE International Conference on Parallel and Distributed Systems
(PDCS-95), Sept. 20-23, 1995, Orlando, Florida, USA, pp. 268-274.
59. Abd-El-Barr, M. H. and Abed, Osama,
"Fault-Tolerance and Terminal Reliability for a Class of Data Manipulator
Networks", IEEE 37th
Midwest Symposium on Circuits and Systems, August 3-5 1994, Lafayette,
Louisiana, U.S.A. pp. 225-229.
60. A. J. Jain, Abd-El-Barr, M. H., and R.
J. Bolton, "Multiple-Valued Logic Function Realization", IEEE International
Symposium on Multiple-Valued Logic (ISMVL), May 22-25, 1995, Indiana
University, Bloomington, USA, pp. 216-221.
61. H. ElGebaly, Abd-El-Barr, M. H., and C. McCrosky, "Architecture
Tradeoffs in Reduced Instruction Set Computers: A Case Study", IEEE
Pacific Rim 1995 Conference, May 17-19, 1995, Victoria, BC, Canada, pp. 78-81.
62. Abd-El-Barr, M. H., and Hai, M. A.,
"Subcube Reliability of a Modular Fault Tolerant Hypercube
Architecture" (ABSTRACT), Conference on Parallel and Distributed
Computing, March 13-15, 1995, Kuwait University, Kuwait, p. 2.
63. Abdel-Hamid, G., and Abd-El-Barr, M.,
"Decomposition-Based Synthesis of Multi-Valued Functions for Threshold
Logic Networks Realization", IEEE International Symposium of
Multiple-Valued Logic (ISMVL), held May 1994, Boston, pp. 59-64.
64. L. Ghatraju, Abd-El-Barr, M. H., and C.
McCrosky, "High-Level Synthesis of Digital Circuits by Finding
Fixpoints", European Design and Test Conference (EDAC' 94), Feb. 1994 pp.
94-98.
65. W. Li, Abd-El-Barr, M. H., and C. McCrosky,
"Reducing the cost of test pattern generation by information
re-using", International Conference on Computer Design: VLSI in Computers
& Processors (ICCD'93), October 3-6, 1993, Cambridge, Massachusetts, USA.
Number of manuscript pages is 18.
66. A. Atul, R. Bolton, Abd-El-Barr, M. H.,
and C. Cheung, "On Multiple-Valued Logic Design of Neural Networks",
36th Midwest Symposium
on Circuits and Systems", August 16-18, 1993, Detroit, Michigan, USA, pp.
1489-1492.
67. Y. Xu, Abd-El-Barr, M. H., and C. McCrosky,
"A Deductive Method for Simulating Transistor Stuck-Open Faults in CMOS
Circuits", European Test Conference (ETC'93), April 19-24, 1993,
Rotterdam, The Netherlands, pp. 284-291.
68. W. Li, C. McCrosky, and Abd-El-Barr, M.
H., "On The Design and Analysis of Unmatched LFSR Patters Generators in
Pseudorandom Testing", European Conference on Design Automation (EDAC'
93), February 22-25, 1993, Paris, France. pp. 217-222.
69. Abd-El-Barr, M. H., and Li, W.,
"SWIM: A Testability Measure for Switch- and Mixed-Level CMOS
Circuits" International Conference on Microelectronics (icm'93) Dec.
14-16, 1993, Dhahran, Saudi Arabia, pp. 9-15.
70. El-Gebaly, H., and Abd-El-Barr, M. H.,
"On concurrent Error Detection of transient Faults in Hard-wired Control
Units" International Conference on Microelectronics (icm'93), Dec. 14-16,
1993, Dhahran, Saudi Arabia, pp. 253-256.
71. Bachtiar, T. M., and Abd-El-Barr, M. H.,
"Logical Neighborhood Network for Fault-Tolerance in Packet Switching
Networks" International Conference on Microelectronics (icm'93), Dec.
14-16, 1993, Dhahran, Saudi Arabia, 287-293.
72. McCrosky, C., Abd-El-Barr, M. H.,
"Synthesis of VLSI Circuits from Parallel Distributed Behavioral
Specifications", Proc. CCVLSI'93, Nov. 14-16, 1993, Banff, Canada, pp.
6B-1:6B-6.
73. Ghatraju, K., Abd-El-Barr, M. H.,
McCrosky, C., "Frontiers for High-Level Synthesis of Digital
Circuits", Proc. CCVLSI'93, Nov. 14-16, 1993, Banff, Canada, pp.
7-15:7-21.
74. Ekong, D. U., Abd-El-Barr, M. H., and
Wood, H. C., "Design of Fault-Tolerant Neurocontrollers using immunization
Techniques", IEEE International Conference on Neural Networks (ICNN'93),
March 28-April 1, 1993, San Francisco, California, pp. 1295-1300.
75. Abd-EL-Barr, M. H., R. J. Bolton, and A.
J. Jain, "Current-Mode CMOS Realization of a Multi-Valued Logic
Neurode", IEEE WESCANEX'93, May 17-18, 1993, Saskatoon, Saskatchewan,
Canada, pp. 201-207.
76. Ekong, D. U., Abd-El-Barr, M. H., and
Wood, H. C., "Fault-tolerant Neural Networks for Control Systems",
IEEE WESCANEX'93, May 17-18, 1993, Saskatoon, Saskatchewan, Canada, pp.
269-275.
77. Abd-El-Barr, M. H., and Choy, H.,
"Incremental Gate: A method to compute minimal cost CCD realization of MVL
functions", Proc. 22nd
IEEE International Symposium on Multiple-valued Logic (ISMVL) , Sendi
Japan, May 27-29, 1992, pp. 111-118.
78. Abd-El-Barr,
M. H., and Mahroos, M., "On the synthesis of MVL functions for
current-mode CMOS circuit implementation", Proc. 22nd IEEE (ISMVL), Sendi Japan, May 27-29,
1992, pp. 221-228.
79. A. Jain, R.
J. Bolton, and M. H. Abd-El-Barr, "Current-mode CMOS Realization of MVL
Operators", Proc. Canadian Conference of Very Large Scale Integration
(CCVLSI), Nova Scotia, Canada, Oct. 18-20, 1992, pp. 276-283.
80. Abd-El-Barr,
M. H., Choy, H., Jain, A., and Bolton, R., "A Comparative Study of
Programmable Realization Techniques of Multi-Valued Multi-Threshold
Functions", Proc. 21st t IEEE (ISMVL), Victoria, BC, Canada, May 26-29, 1991, pp. 372-381.
81. Abd-El-Barr,
M. H., Sinkinson, M., and Raafat, H., "A Switch-Level Simulator for CMOS
VLSI Circuits Using Evaluation Nets", 4th International Symposium on IC
Design, Singapore, Sept. 11-13, 1991, pp. 615-621.
82. Jain, A.,
Bolton, R., and Abd-El-Barr, M. H., "A New TSUM-based Minimization
Technique for MVL Function Implementation using Current-mode CMOS", 4th International Symposium on IC Design,
Singapore, Sept. 11-13, 1991, pp. 622-627.
83. Mahroos, M.
I., and Abd-El-Barr, M. H.,"IDSAC: An AI Approach to Systolic Arrays
Synthesis", International Conference on Microelectronics (ICM'91), Cairo,
Egypt, Dec. 21-23, 1991, pp. 144-147.
84. Abd-El-Barr,
M. H., and Bachtiar, M., "Reliability and Yield Enhancement of WSI Array
Processors through Wafer Stacking", International Conference on
Microelectronics (ICM'91), Cairo, Egypt, Dec. 21-23, 1991, pp. 92-95.
85. Abd-El-Barr,
M. H. and Choy, H., "On the Synthesis of MVMT Functions for PLA
Implementation Using CCDs", Proc. 20th ISMVL, Charlotte, N.C., May 23-25 1990,
pp. 316-323.
86. Abd-El-Barr,
M. H. and Raafat, H. M., "A New VLSI Architecture for Texture Distance Computation",
Proc., 1st International Conference on Microelectronics (ICM'90), October
13-15, 1990, Damascus, Syria, pp. 2.6.1-2.6.6.
87. Zaky, S.
G., Vranesic, Z. G., and Abd-El-Barr, M. H., "Step-wise Synthesis of CCD
MVL Functions", Proc. 20th IEEE (ISMVL), Charlotte, N.C., May 23-25 1990, pp. 300-307.
88. Bachtiar,
M. and Abd-El-Barr, M. H., "A Two-level Reconfiguration Fault-Tolerant
Technique for Processor Arrays", Proc., 1st International Conference on
Microelectronics (ICM'90), October 13-15, 1990, Damascus, Syria, pp.
2.30.1-2.30.6.
89. Tandri, S.,
M. H. Abd-El-Barr, and C. McCrosky, "High Level Specification, Simulation,
and Fabrication of Systolic/Wavefront Arrays - A Case Study", Proc. 1990
Canadian Conference on VLSI (CCVLSI), October 1990, Ottawa, Canada, pp.
6.6.1-6.6.6.
90. Abd-El-Barr,
M. H. and Vranesic, Z. G., "Programmable Realization of MVMT Functions
using CCDs", Proc. 19th
IEEE (ISMVL), Ghangzhou (Canton), China, May 29-31, 1989, pp. 82-93.
91. G.
Lakshmikanth, Abd-El-Barr, M. H., H. M. Raafat, and R. J. Bolton, "An
Integrated Circuit For Texture Distance Computation", 1989 IEEE ASIC,
Rochester, N.Y., Sept. 25-28, 1989, pp. P8-4.1-P8-4.6.
92. A.
Jalnapurkar, H. C. Wood, and Abd-EL-Barr, M. H., "High Reliability
Microcomputers for Power System Control", Proc. Canadian Conference on
Electrical and Computer Engineering, Nov. 1988, Vancouver, pp. 746-750.
93. M.
Giridhar, S. Tandri, Abd-El-Barr, M. H., and H. M. Raafat, "VLSI Systolic
Implementation of the Transportation Simplex Algorithm for Texture Distance
Computation", Proc. IEEE 1988 International Conference on Systems, Man,
and Cybernetics, Aug. 1988, China, pp. 1136-1140.
94. Abd-El-Barr,
M. H., T. D. Hoang, and Z. G. Vranesic, "The Incremental-Cost Approach for
Synthesis of 4-valued Unary Functions", Proc. 18th IEEE (ISMVL,
May 1988, pp. 82-90. (This paper won the Certificate for Best Paper during
the 18th ISMVL held in Spain, May 1988).
95. Abd-El-Barr,
M. H., Z. G. Vranesic and S. G. Zaky, "Synthesis of Multi-Valued Logic
Functions for CCD Implementation", Proceedings of IEEE 16th ISMVL, May 1986, pp. 116-127.
96. Abd-El-Barr,
M. H., Z. G. Vranesic and S. G. Zaky, "Design and Applications of Binary
and Multi-Valued CCD Circuits", Proceedings 16th ISMVL, May 1986, pp. 137-144.
97. Abd-El-Barr,
M. H., Z. G. Vranesic and S. G. Zaky, "Realization of Multi-Valued
Multi-Threshold Logic Functions Using CCDs", Proceedings 15th ISMVL, May 1985, pp. 126-136. (This
paper was selected by IEEE TC for publication in the special issue of the IEEE
Trans. Comput. published Feb. 1986, see list of journal papers for details).
98. Abd-El-Barr,
M. H. and Z. G. Vranesic, "4-Valued 2-Attribute MOS Encoder and Decoder
Circuits Design", Proc. 15th ISMVL, May 1985, pp. 323-330.
99. M. S.
Metwally, M. R. Elkaraksy, A. S. Noah and M. H. Abd-El-Barr, "Modeling and
Simulation of a Multi-Microprocessor-Based Interface Scheme", Proceedings
13th annual Pittsburgh
Conference on Modeling and simulation, Pittsburgh, April 1982, pp. 831-838.
100.
Y. M. Ajabnoor and M. H. Abd-El-Barr, "Stuck-type
Fault Detection In Multi-Valued Combinational Circuits", Proc. 11th ISMVL, May 1981, pp. 275-282.
101.
M. R. Elkaraksy, A. S. Noah, and M. H. Abd-El-Barr,
"Communication Channels Microprocessor-based Interface for Bit-Oriented
Line Protocols", Proceedings 8th International Symposium on Mini- and Micro-Computers, May
1979, pp. 167-169.
Books
1. Abd-El-Barr,
M., “Design and Analysis of Reliable and Fault Tolerant Computer Systems”, in
Progress (A total of 12 Chapters, FOUR have already been written). A contarct
has been signed with Imperial College Press (IPC), August 2, 2002. Expected
date of book delivery is Sept. 30, 2003.
2. Abd-El-Barr,
M., K. Elleithy, and H. El-Rewini, “Computer Organization and Architecture”, in
Progress (A total of 20 chapters, six chapters are already written). FOUR revised
sample chapters are now under reconsideration by Prentice-Hall Publishing Co.,
July 2002.
3. Abd-El-Barr,
M., “Digital Systems Testing: Theory and Practice”, in Progress, (Twenty
chapters, Six chapters are already written). No communications with publishers
as of now.
Non-Refereed
Publications
1. Abd-El-Barr,
M. H., and A. K. Jain, "CAD Tools for VLSI Design: A User Guide",
Department of Computational Science, University of Saskatchewan, Laboratory
Notes. Number of pages is 172. First release 1992.
2. F. Ashraf, M.
H. Abd-El-Barr, and K. Al-Tawil, “Introduction to Routing in Multicomputer
Networks”, Computer Architecture News, ACM SIGARCH, vol. 26, no. 5, pp. 14-21,
December 1998.
Technical
Reports
1. Abd-El-Barr,
M. H. and Muhammad Nayyar Hasan, "An Output Cyclic Technique for
Minimization of MVL Functions", College of Computer Sciences and
Engineering, King Fahd University of Petroleum and Minerals (KFUPM), report
KFUPM-CCSE-97-007(COE).
2. Abd-El-Barr,
M. H., Gamal Abdul Hamid, and Muhammad Nayyar Hasan, "On the Synthesis of
MVL Functions using Input and Output Assignments", College of Computer
Sciences and Engineering, King
Fahd University of Petroleum and Minerals (KFUPM), report KFUPM-CCSE-97-008(COE).
3. Henry
Fernandes and Abd-El-Barr, M. H., "A Modular Approach for Synthesis of
MVMDDs Using Current-Mode CMOS", College of Computer Sciences and
Engineering, King Fahd University of Petroleum and Minerals (KFUPM), report
KFUPM-CCSE-97-009 (COE).
4. Abd-El-Barr,
M. H., T. D. Hoang, and Z. G. Vranesic, "The Incremental-Cost Approach for
Synthesis of CCD 4-valued Unary Functions", Department of Computational
Science, University of Saskatchewan, report 87-10, October 1987.
5. Abd-El-Barr,
M. H., "New Algorithmic Synthesis Techniques for MVL Functions",
Department of Computational Science, University of Saskatchewan, report 87-6,
May 1987.
6. Abd-El-Barr,
M. H., "Less Expensive CCD Realization of MVMT Functions", Department
of Computational Science, University of Saskatchewan, report 87-7, May 1987.
7. M. R.
Elkaraksy, A. S. Noah and M. H. Abd-El-Barr, "Simulating a
Multi-microprocessor-Based Interface Using Evaluation Nets", Research
Report No. EE-3(1402), March 1982, College of Engineering, Riyadh University.
8. M. R.
Elkaraksy, A. S. Noah and M. H. Abd-El-Barr, "Associating Microprocessor
Based Interface to Communication Networks Nodes", Research Report No.
CE-1(99), March 1979, College of Engineering, Riyadh University.
9. M. R.
Elkaraksy, A. S. Noah and M. H. Abd-El-Barr, "Microprocessors for Data
Communications", Research Report No. CE-4(98), June 1978, College of
Engineering, Riyadh University.
10. M. R.
Elkaraksy, A. S. Noah and M. H. Abd-El-Barr, "Communication Lines Control
and Control Procedure", Research Report, No. CE-2(98), June 1978, College
of Engineering, Riyadh University.