By: Masud-ul-Hasan
12
TCON : Counter/Timer CONtrol Register (088H)
•- TF1, TF0 : Overflow flags for Timer 1 and Timer 0. *
-- TR1, TR0 : Run control bits for Timer 1 and Timer 0. *
Set to run, reset to hold.
•
•- IE1, IE0 : Edge flag for external interrupts 1 and 0.
• Set by interrupt edge, cleared when interrupt is processed.
•- IT1, IT0 : Type bit for external interrupts.
• Set for falling edge interrupts, reset for 0 level interrupts.
•
•* = related to counter/timer operation
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timers
Interrupts