Notes

Outline

Chapter 2 Hardware Summary (I. Scott Mackenzie)

The 8051 A Microcontroller derivative family based on the 8051 core. A Microcontroller because a one-chip system can be made with the one chip containing: Program & Data Memory I/O Ports Serial Communication Counters/Timers Interrupt Control logic A-to-D and D-to-A converters & so on ...

MCS-51 Family Overview Term 8051 refers to MCS-51 family of microcontroller ICs by Intel Corp. (From 8031-8752) Features are summarized below: 8 Bit data path and ALU. Easy interfacing. 12 to 30 MHz versions available. (1 µsec to 400 ns for single cycle instructions). Full instruction set including: Multiply and Divide. Bit set, reset, and test (Boolean instructions). Variety of addressing modes.

Hardware Features of the 8051

8051 Block Diagram

8051 Pin Outs

I/O Ports - Four 8-bit I/O ports. - Most have alternate functions. - Bi-directional.

Port 0 (pin 32-39) Dual purpose I/O port. In min. component design, it is used as a general purpose I/O port. - In larger designs with external memory, it becomes a multiplexed data bus: 8-bit instruction bus, strobed by PSEN. Low byte of address bus, strobed by ALE. 8-bit data bus, strobed by WR and RD.

Port 1 (pin 1-8) - As an I/O port: Standard bi-directional port for interfacing to external devices as required for I/O. - Alternate functions: Only on some derivatives.

Port 2 (pin 21-28) Dual purpose I/O port. As an I/O port: Standard bi-directional general purpose I/O port. - Alternate functions: High byte of address bus for external program and data memory accesses.

Port 3 (pin 10-17) - Dual purpose I/O port. As an I/O port: Standard bi-directional general purpose I/O port. - Alternate functions: Serial I/O - TXD, RXD Timer clocks - T0, T1 Interrupts - INT0, INT1 Data memory - RD, WR

8051 has 4 Bus Control Signals PSEN (pin 29): (Program Store Enable) enables external program (code) memory. Usually connected to EPROM’s output enable (OE). It pulses low during fetch stage of an instruction. It remains high while executing a program from internal ROM. ALE (pin 30): (Address Latch Enable) used for demultiplexing the address and data bus when port 0 is used as the data bus and low-byte of address bus. EA (pin 31): (External Access) high to execute programs from internal ROM and low to execute from external memory only. RST (pin 9): (RESET) master reset of 8051.

Reset External reset is asynchronous to the internal clock. RST pin must be high for at least two machine cycles while the oscillator is running. Internal RAM is not affected by reset. Reset sets PC to 0000H. Typical circuits:

8051 Oscillator & Power Pins Pins 18 and 19 are the oscillator pins to connect the crystal of nominal frequency 12 MHz. Pin 40 is for +5V and pin 20 is for GND.

Addressing Space 64K x 8 ROM - External Program Memory. (Enabled via PSEN) - 64K x 8 RAM - External Data Memory. (Enabled via RD and WR) - 256 x 8 RAM - Internal Data Memory. - 128 x 8 Special Function Registers (SFRs). - Bit addressing of 16 RAM locations      and 16 SFRs.

Internal Data Memory - Four register banks (Register Bank 0-3): 00 to 1F hexadecimal. - Bit addressable RAM (128 bits): 20 to 2F hexadecimal. - General purpose RAM (directly addressable range): 30 to 7F hexadecimal. - Special function registers (indirectly addressable range): 80 to FF hexadecimal.

Internal Data Memory

"Any location on general purpose..." Any location on general purpose RAM can be accessed freely using direct or indirect addressing modes. E.g., MOV A, 5FH ;contents of 5FH location will be loaded in A E.g., MOV R0, #5FH ; value 5FH will be loaded in register R0   MOV A, @R0 ; data will be loaded in A which is pointed   ; at by R0 Powerful feature that bits can be set, cleared, ANDed, ORed, etc. with a single instruction  E.g., SETB 67H  ; to set bit 67H Most microprocessors will do like   MOV A, 2CH ; read entire byte   ORL A, #10000000B ; set MSB MOV 2CH, A ; write back entire byte

External Bus Expansion PORT 2 PORT 0 ALE P3.7 P3.6 PSEN

External Program Memory

External Data Memory ·  64K byte address space. ·  Indirectly addressable via R0 and R1 in 256 byte segments. ·  Entire space in indirectly addressable via the data pointer DPTR.

Special Function Register Space - 128  byte address space, directly addressable as 80 to FF hex. - 16 addresses are bit addressable: Set, Clear, AND, OR, MOV (those ending with 0 or 8). - This space contains: Special purpose CPU registers. I/O control registers. I/O ports.

Special Function Register Map F8 F0 B E8 E0 ACC D8 D0       PSW C8 C0 B8 IP B0 P3 A8 IE A0     P2 98      SCON     SBUF 90 P1 88 TCON TMOD TL0 TL1 TH0 TH1 80 P0 SP DPL DPH PCON

Special Function Registers CPU registers: - ACC : Accumulator. - B : B register. - PSW : Program Status Word. - SP : Stack Pointer. - DPTR : Data Pointer (DPH, DPL). Interrupt control: -IE : Interrupt Enable. -IP : Interrupt Priority. I/O Ports: - P0 : Port 0. - P1 : Port 1. - P2 : Port 2. - P3 : Port 3.

Special Function Registers (cont'd) Timers: - TMOD : Timer mode. - TCON : Timer control. - TH0 : Timer 0 high byte. - TL0 : Timer 0 low byte. - TH1 : Timer 1 high byte. - TL1 : Timer 1 low byte. Serial I/O: - SCON : Serial port control. - SBUF : Serial data registers. Other: - PCON : Power control

PSW : Program Status Word CY         AC         F0         RS1         RS0        OV       ----       P - CY : Carry Flag. - AC : Auxiliary Carry Flag. - F0 : Flag 0 (available for user). - RS1 : Register Select 1. - RS0 : Register Select 0. - OV : Arithmetic Overflow Flag. - P : Accumulator Parity Flag.

PSW (Program Status Word) CY: (Carry Flag) is dual purpose: (1) As traditional CY for arithmetic operations e.g., If A contains FFH then the instruction ADD A, #1 leaves A equal to 00H and sets the CY in PSW. (A=00H & CY=1) (2) As Boolean accumulator e.g., ANL C, 25H ; ANDs bit 25H with the carry flag and places the result back in the CY. AC: (Auxiliary Carry Flag) used in addition of BCD numbers, is set if a carry was generated out of bit 3 into bit 4. If the values are added are BCD, then the add instruction must be followed by DAA (decimal adjust accumulator) to bring results greater than 9 back into range. F0: (Flag 0) is a general-purpose flag bit available for user applications.

PSW(Contd.) OV: (Overflow flag) is set after an addition or subtraction operation if there was an arithmetic overflow. Results greater than +127 or less than –128 will set OV bit. P: (Parity Bit) automatically set or cleared each machine cycle to establish even parity with the accumulator. Parity bit is most commonly used in conjunction with serial port routines to include a parity bit before or after the transmission. RS1 & RS0 are used to select different register banks.

SFRs (Special Function registers) B Register: (at F0H) also bit addressable and used along with the accumulator for multiply & divide operations. E.g., MUL A B instruction multiplies the 8-bit unsigned values in A & B and leaves the 16-bit result in A (low-byte) & B (high-byte) E.g., DIV A B instruction divides A by B leaving the integer result in A and remainder in B. SP: (Stack Pointer) (at 81H) is an 8-bit register contains the address of the data item currently on the top of stack. Its operations include “Pushing” & “Popping” data from the stack. DPTR: (Data Pointer) is 16-bit register at 82H (DPL, low-byte) and 83H (DPH, high-byte) used to access external code or data memory. It can be specified by its 16-bit name, DPTR, or by each individual byte name, DPH and DPL.