| ID | Task Name | Duration | Start | Finish | Resource Names | % Complete |
|---|
| 1 | Prepare an action plan | 5 days | Tue 3/5/02 | Mon 3/11/02 | Group | 0% |
| 2 | Problem analysis and survey of different options | 7 days | Tue 3/12/02 | Wed 3/20/02 | Group | 0% |
| 3 | System Design and Segmentation | 7 days | Sat 3/23/02 | Sun 3/31/02 | Group | 0% |
| 4 | Design of the Control unit | 0 days | Tue 4/23/02 | Tue 4/23/02 | | 0% |
| 5 | Selection of a control scheme | 3 days | Mon 4/1/02 | Wed 4/3/02 | Ahmad | 0% |
| 6 | Logic Design of CU | 4 days | Sat 4/6/02 | Tue 4/9/02 | Ahmad | 0% |
| 7 | FPGA synthesis of CU | 4 days | Wed 4/10/02 | Mon 4/15/02 | Ali | 0% |
| 8 | CU Testing | 5 days | Tue 4/16/02 | Mon 4/22/02 | Ali | 0% |
| 9 | Design of the execution unit | 0 days | Tue 4/23/02 | Tue 4/23/02 | | 0% |
| 10 | Data path design | 5 days | Tue 4/9/02 | Mon 4/15/02 | Ahmad | 0% |
| 11 | Design of the register file | 4 days | Wed 4/10/02 | Mon 4/15/02 | Ali | 0% |
| 12 | Design of the Bus arbitration Unit | 4 days | Wed 4/10/02 | Mon 4/15/02 | Ahmad | 0% |
| 13 | Design of the TLB unit | 5 days | Sun 5/12/02 | Sat 5/18/02 | Ali | 0% |
| 14 | Integration of the EU | 5 days | Tue 4/16/02 | Mon 4/22/02 | Ali | 0% |
| 15 | System Integration | 6 days | Tue 4/23/02 | Tue 4/30/02 | Group | 0% |
| 16 | Testing and Debuging | 6 days? | Wed 5/1/02 | Wed 5/8/02 | Group | 0% |
| 17 | Final Report | 6 days | Sat 5/11/02 | Sat 5/18/02 | Group | 0% |