COE360, Quiz # 3 (Take home)

Dr. Muhammad Elrabaa

 

 

For the CMOS inverter shown, and using WinSpice and the 0.5 U technology, obtain the device sizes such that:

 

  1. The logical threshold is = 2.75 V (this is the input voltage that makes the output = 2.5V)
  2. The area is minimum (i.e. device sizes are minimum) such that the delay is 120 pS.

 

 

 

 

 

 

 

 

 

 

 

 

 

 


Solution hints:

 

1.     First determine the required ratio between Wp and Wn to get the required logical threshold – do a dc sweep, keeping Wp constant while changing Wn to get this ratio.

2.     Now, while keeping the ratio between Wp and Wn constant at the value found in the 1st step, increase both of them and do a transient analysis. Choose the minimum set of Wp and Wn values that give you a 120 pS delay.