8 years of industrial experience at National Semiconductor Corporation, a large and leading multi-national Integrated Circuit manufacturer with headquarters in Santa Clara California (Silicon Valley).

Wide experience in the field of VLSI Integrated Circuit design in general and in MOS Memory Design in particular.

Have been involved in all phases of the design cycle of VLSI Integrated Circuits, including product performance specification, process technology definition, circuit design and layout, logic and device level simulation, test requirements, circuit debugging and troubleshooting as well as final testing.

Design of 32K CMOS EPROM,

Design of 64K NMOS EPROM,

Design of 256K NMOS DRAM,

Design of 256K CMOS EPROM, (Project leader)

Design of 1MB EPROM, and (Project leader)

Design of 256K CMOS FLASH EEPROM (Project Leader)

Design of a CMOS SRAM-Based FPGA Test chip