
Journal Publications

Ahmad
Shawahna, Sadiq M. Sait, and Aiman ElMaleh, “FPGA based
Accelerators of Deep Learning Networks for Learning and
Classification: A Review,” IEEE Access, Vol. 7, Iss. 1, pp.
78237859, 2019. [IF=3.557, Q1]

Ghashmi H. Bin Talib, Aiman H. ElMaleh, and Sadiq M. Sait, “Design
of Fault Tolerant Adders: A Review,” The Arabian Journal for Science
and Engineering, 2018. [IF=1.092, Q3]

Ahmad T. Sheikh, Aiman H. ElMaleh, "Double Modular Redundancy (DMR)
Based Fault Tolerance Technique for Combinational Circuits," Journal of
Circuits, Systems, and Computers, Volume No.27, Issue No. 6, 2018. [IF=0.595,
Q4]

Aiman H. ElMaleh, "A Finite State Machine Based Fault Tolerance
Technique with Enhanced Area and Power of Synthesized Sequential
Circuits," IET Computers & Digital Techniques, Volume
11, Issue 4, July
2017, pp. 159 – 164. [IF=0.639, Q4]

Ahmad T. Sheikh, Aiman H. ElMaleh, "An Integrated Fault
Tolerance Technique for Combinational Circuits Based on Implications and
Transistor Sizing," Integration, the VLSI Journal,
Volume 58, June 2017, pp.
35–46. [IF=0.904, Q4]

Aiman H. ElMaleh, "A Probabilistic Pairwise Swap Search State
Assignment Algorithm for Sequential Circuit Optimization," Integration,
the VLSI Journal,
Volume 56, Jan. 2017, pp.
32–43. [IF=0.904, Q4]

Ahmad T. Sheikh, Aiman H. ElMaleh, Muhammad E.S. Elrabaa, and
Sadiq M. Sait, "A Fault Tolerance Technique for Combinational Circuits
Based on SelectiveTransistor Redundancy," IEEE Transactions on VLSI,
Vol. 25, Iss. 1, Jan. 2017, pp. 224237. [IF=1.744,
Q2]

Muhammad E. S. Elrabaa, Amran AlAghbari, Mohammad AlAsli,
Aiman ElMaleh, Abdelhafid Bouhraoua, Mohammad Alshayeb, "A lowcost
Platform for the Prototyping and Characterization of Digital Circuit
IPs," Integration, the VLSI Journal,
Volume 54, June 2016, Pages
1–9. [IF=0.904, Q4]

Aiman H. ElMaleh, "MajorityBased Evolution State Assignment
Algorithm for Area and Power Optimization of Sequential Circuits," IET
Computers & Digital Techniques, Vol. 10, Iss. 1, pp. 30–36, 2016. [IF=0.639,
Q4]

Sadiq M. Sait, Abubakar Bala, Aiman H. ElMaleh, "Cuckoo Search
Based Resource Optimization of Datacenters," Applied Intelligence, April
2016, Volume 44, Issue 3, pp
489506. [IF=1.983, Q2]

Aiman H. ElMaleh and Khaled A.K. Daud, "SimulationBased Method
for Synthesizing Soft Error Tolerant Combinational Circuits," IEEE
Transactions on Reliability, Volume 64, Issue
3, Sep. 2015, Pages 935 
948. [IF=2.729, Q1]

Aiman H. ElMaleh, Sadiq M. Sait, Abubakar Bala, "State
Assignment for Area Minimization of Sequential Circuits Based on Cuckoo
Search Optimization," Computers & Electrical Engineering,
Volume 44, May 2015, Pages
13–23. [IF=1.747, Q2]

Mohammad Alshayeb, Muhammad E. S. Elrabaa, Ayman Hroub, Amran AlAghbari,
Aiman H. ElMaleh and Abdelhafid Bouhraoua, “Towards a Test Definition
Language for Integrated Circuits,” Journal of Circuits, Systems, and
Computers, Volume No.24, Issue No. 3, 2015. [IF=0.595,
Q4]

Aiman H. ElMaleh, Ayed S. AlQahtani, “A Finite State Machine
Based Fault Tolerance Technique for Sequential Circuits,”
Microelectronics Reliability, Volume 54, Issue 3, March 2014, Pages
491662. [IF=1.236, Q3]

Aiman H. ElMaleh, Feras Chikh Oughali, “A Generalized Modular
Redundancy Scheme for Enhancing Fault Tolerance of Combinational
Circuits,” Microelectronics Reliability,
Volume 54, Issue 1, January
2014, Pages 316–326. [[IF=1.236, Q3]

Aiman H. ElMaleh, Ahmad T. Sheikh and Sadiq M. Sait, “Binary
Particle Swarm Optimization (BPSO) Based State Assignment for Area
Minimization of Sequential Circuits,” Applied Soft Computing,
Volume 13, Issue 12, December
2013, Pages 4832–4840. [IF=3.907, Q1]

Sadiq M. Sait, Ahmad T. Sheikh, Aiman H. ElMaleh, “Cell
Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid
Algorithm,” Journal of Applied Research and Technology, Vol. 11, October
2013, pp. 653664. [IF=0.447, Q4]

Aiman H. ElMaleh, Mohamed Adnan Landolsi and Esa A. AlGhoneim,
“WindowConstrained InterconnectEfficient Progressive Edge Growth LDPC
Codes,” International Journal of Electronics and Communications,
Volume 67, Issue 7, July
2013, Pages 588–594. [IF=2.115, Q2]

Wenfa Zhan and Aiman H. ElMaleh, " A New Scheme of Test Vector
Compression Based on EqualRunLength Coding (ERLC)," Integration, the
VLSI Journal, Vol. 45, pp. 9198, 2012. [IF=0.904,
Q4]

Aiman ElMaleh,
Saif al Zahir and
Esam Khan, “Test data
compression based on geometric shapes,”
Computers & Electrical Engineering,
Vol. 37, Issue 3, May 2011,
Pages 376391. [IF=1.747, Q2]

Esa Alghonaim, Aiman ElMaleh, M. Adnan Landolsi and Sadiq M. Sait, “A Platform for LDPC Code Design and Performance Evaluation,” The
Arabian Journal for Science and Engineering, Vol. 35, No. 2B, 2010, pp.
131148. [IF=1.092, Q3]

Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman
ElMaleh, “A scheme of test data compression based on coding of even
bits marking and selective output inversion,” Computers and Electrical
Engineering 36 (2010), pp. 969977. [IF=1.747,
Q2]

Aiman ElMaleh, Bashir M. AlHashimi, Aissa Melouki and Farhan
Khan, "Defect
Tolerant N^{2}Transistor Structure for Reliable Nanoelectronic
Designs,"
IET Computers & Digital
Techniques (Special Issue on Nanoelectronics), Vol. 3, Iss. 6, pp.
570580, Nov. 2009. [IF=0.639, Q4]

Aiman ElMaleh, Mustafa I. Ali and Ahmad A. AlYamani, "Reconfigurable
Broadcast Scan Compression Using Relaxation Based Test Vector
Decomposition," IET Computers
& Digital Techniques, Vol. 3, Iss. 2, pp. 143–161, March 2009. [IF=0.639,
Q4]

Esa Alghonaim, Aiman ElMaleh and Adnan AlAndalusi, "NEW
TECHNIQUE FOR IMPROVING PERFORMANCE OF LDPC CODES IN THE PRESENCE OF
TRAPPING SETS," EURASIP Journal on Wireless Communications and
Networking, Article ID 362897, 12 pages, 2008. doi:10.1155/2008/362897
(A special issue on Advances in Error Control Coding Techniques). [IF=2.407,
Q2]

Aiman ElMaleh, "Efficient
Test Compression Technique Based on Block Merging,"
IET Comput. Digit. Tech., 2008, Vol. 2, No. 5, pp. 327–335. [IF=0.639,
Q4]

Aiman ElMaleh, “Test Data Compression for SystemonaChip using
Extended FrequencyDirected RunLength (EFDR) Code,” IET Computers &
Digital Techniques, 2008, Vol. 2, No. 3, pp. 155–163. [IF=0.639,
Q4]

Aiman ElMaleh, Saqib Khurshid, “Efficient Test Compaction for
Combinational Circuits Based on Fault Detection CountDirected
Clustering,” IET Computers & Digital Techniques, 2007, 1, (4), pp.
364–368. [IF=0.639, Q4]

Aiman ElMaleh, Saqib Khursheed, and Sadiq Sait, “Static
Compaction Techniques for Sequential Circuits Based on Reverse Order
Restoration and Test Relaxation” IEEE TRANSACTIONS ON COMPUTERAIDED
DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 11, NOVEMBER
2006, pp. 25562564. [IF=2.089, Q2]

Sadiq M. Sait, Aiman H. ElMaleh, and Raslan H AlAbaji,
“Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning,”
ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 19 (3), APR 2006,
pp. 257268. [IF=2.819, Q1]

Aiman ElMaleh, Sadiq Sait, and Syed Shazli, “Evolutionary
Algorithms for State Justification in Sequential Automatic Test Pattern
Generation,” ENGINEERING INTELLIGENT SYSTEMS FOR ELECTRICAL ENGINEERING
AND COMMUNICATIONS 13 (1): 1521, MAR 2005. [IF=0.205,
Q4]

Aiman ElMaleh and Khaled AlUtaibi, “An Efficient Test
Relaxation Technique for Synchronous Sequential Circuits,”
IEEE Transactions on Computer Aided Design of
Integrated Circuits, Vol. 23, No. 6, pp. 933940, June 2004. [IF=2.089,
Q2]

Aiman ElMaleh and Yahya Osais, "Test Vector Decomposition Based
Static Compaction Algorithms for Combinational Circuits", ACM
Transactions on Design Automation of Electronic Systems, Volume 8, No.
4, pp. 430459, October 2003. [IF=0.87, Q4]

Aiman ElMaleh, Thomas Marchok, Janusz Rajski, and Wojciech Maly,
“Behavior and Testability Preservation Under the Retiming
Transformation,” IEEE Transactions on ComputerAided Desig, Vol. 16, pp.
528543, May 1997. [[IF=2.089, Q2]

Thomas Marchok, Aiman ElMaleh, Wojciech Maly, and Janusz Rajski,
“A Complexity Analysis of Sequential ATPG,” IEEE Transactions on
ComputerAided Design, Vol. 15, pp. 14091423, Nov. 1996. [IF=2.089,
Q2]

Aiman ElMaleh and Janusz Rajski, “Delay Fault Testability
Preservation of the Concurrent Decomposition and Factorization
Transformations,” IEEE Transactions on ComputerAided Design, Vol. 14,
pp. 582590, May 1995. (A special section on 12th IEEE VLSI Test
Symposium.) [IF=2.089, Q2]

Thomas Marchok, Aiman ElMaleh, Janusz Rajski, and Wojciech Maly,
“Testability Implications of Performance Driven Logic Synthesis,’’ in
IEEE Design and Test of Computers, pp. 3239, summer 1995.(A special
issue on First International Test Synthesis Workshop.) [IF=1.623,
Q2]

Sadiq M. Sait and Aiman H. ElMaleh, “State Machine Synthesis
with Weinberger Arrays,” Int. Journal of Electronics, Vol. 71, No. 1,
pp. 112, July 1991. [IF=0.939, Q4]
Conference Publications

Aiman H. ElMaleh, "A
Sequential Circuit Fault Tolerance Technique with Enhanced Area and Power," 15th IEEE International
Symposium on Signal Processing and Information Technology, pp. 301304,
2015.

Aiman H. ElMaleh, "State Assignment for Power Optimization of
Sequential Circuits based on a Probabilistic Pairwise Swap Search
Algorithm," 15th IEEE International Symposium on Signal Processing and
Information Technology, pp. 305308, 2015.

Aiman H. ElMaleh, Feras Chikh Oughali, “Enhancing Reliability of
Combinational Circuits against Soft Errors by Using a Generalized
Modular Redundancy Scheme,” 2013 International Symposium on Electronic
System Design, pp. 6266.

Wenfa Zhan and Aiman H. ElMaleh, "A New Collaborative Scheme of
Test Vector Compression Based on EqualRunLength Coding (ERLC)," The
13th International Conference on Computer Supported Cooperative Work in
Design (CSCWD 2009), pp.2125, April 2009.

Aiman H. ElMaleh, Bashir M. AlHashimi and Aissa Melouki,
"TransistorLevel Based DefectTolerance for Reliable Nanoelectronics,"
The sixth ACS/IEEE International Conference on Computer Systems and
Applications (AICCSA08), Doha, Qatar, 2008 pp. 5360.

Esa AlGhonaim, Aiman H. ElMaleh, and Adnan Andalusi, "Using
input/output queues to increase LDPC decoder performance," The sixth
ACS/IEEE International Conference on Computer Systems and Applications
(AICCSA08), Doha, Qatar, 2008, pp. 304308.

Esa Alghonaim, Aiman ElMaleh and Adnan AlAndalusi, " PARALLEL
COMPUTING PLATFORM FOR EVALUATING LDPC CODES PERFORMANCE," IEEE
International Conference on Signal Processing and Communications (ICSPC
2007), November 2007, Dubai, United Arab Emirates, pp. 157 160.

Esa Alghonaim, Mohamed Adnan Landolsi, and Aiman ElMaleh,
"IMPROVING BER PERFORMANCE OF LDPC CODES BASED ON INTERMEDIATE DECODING
RESULTS," IEEE International Conference on Signal Processing and
Communications (ICSPC 2007), November 2007, Dubai, United Arab Emirates,
pp. 1547 1550.

Aiman H. ElMaleh, Mustafa Imran Ali and Ahmad A. AlYamani, "A
Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based
Test Vector Decomposition," 16th IEEE Asian Test Symposium, Oct. 2007.
pp. 9194.

Aiman ELMALEH, Bashir
ALHASHIMI, Ahmad ALYAMANI, “DefectTolerant N^{2}Transistor
Structure for Reliable Design at the Nanoscale,” IEEE European Test
Symposium 2007, Freiburg, Germany.

Aiman ElMaleh, Saqib Khurshid, “Efficient Test Compaction for
Combinational Circuits Based on Fault Detection
CountDirected Clustering,” IEEE Int. Design and Test Workshop, Nov.
1920, UAE, 2006.

Aiman ElMaleh, Basil Arkasosy, M. Adnan AlAndalusi,
“InterconnectEfficient LDPC Code Design,” 18th IEEE Int. Conf. on
Microlelectronics, Dec. 2006, Dhahran, Saudi Arabia, pp. 127130.

Aiman ElMaleh, “An Efficient Test Vector Compression Technique
Based on Block Merging,” IEEE Int. Symp. on Circuits and Systems, pp.
14471450, May 2006.

Aiman ElMaleh, Sadiq M. Sait and Faisal Nawaz Khan, “Finite
State Machine State Assignment for Area and Power Minimization,” IEEE
Int. Symp. on Circuits and Systems, pp. 53035306, May 2006.

Aiman ElMaleh, Saqib Khursheed, and Sadiq Sait, “Static
Compaction Techniques for Sequential Circuits Based on Reverse Order
Restoration and Test Relaxation” IEEE 14th Asian Test Symposium, pp.
378 – 385, Dec. 1821 2005.

Aiman ElMaleh and Yahya Osais, “A Classbased Clustering Static
Compaction Technique for Combinational Circuits,” The 16th International
Conference on Microelectronics, pp. 522–525, 68 Dec. 2004.

Aiman ElMaleh and Yahya Osais, “On Test Vector Reordering for
Combinational Circuits,” The 16th International Conference on
Microelectronics, pp. 772 – 775, 68 Dec. 2004.

Aiman ElMaleh, “A Hybrid Test Compression Technique for
Efficient Testing of SystemsonaChip,” 10th IEEE International
Conference on Electronics, Circuits and Systems, December 2003.

Yahya Osais and Aiman ElMaleh, “A Static Test Compaction
Technique for Combinational Circuits Based on Independent Fault
Clustering,” 10th IEEE International Conference on Electronics, Circuits
and Systems, December 2003.

Sadiq Sait, Aiman ElMaleh and Raslan AlAbaji, "Enhancing
Performance of Iterative Heuristics for VLSI Netlist Partitioning", 10th
IEEE International Conference on Electronics, Circuits and Systems,
December 2003.

Aiman ElMaleh and Khaled AlUtaibi, "An Efficient Test Relaxation Technique for Synchronous Sequential Circuits" Proc. of the
21’th IEEE VLSI Test Symposium (VTS), pp. 179185, 2003.

Aiman ElMaleh and Khaled AlUtaibi, " ON EFFICIENT EXTRACTION OF
PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS "
Proc. of the IEEE International Symposium on Circuits and Systems
(ISCAS), pp. V545  V548, 2003.

Sadiq Sait, Aiman ElMaleh and Raslan AlAbaji, "SIMULATED
EVOLUTION ALGORITHM FOR MULTIOBJECTIVE VLSI NETLIST BIPARTITIONING"
Proc. of the IEEE International Symposium on Circuits and Systems
(ISCAS), pp. V457  V460, 2003.

Sadiq Sait, Aiman ElMaleh and Raslan AlAbaji, "GENERAL
ITERATIVE HEURISTICS FOR VLSI MULTIOBJECTIVE PARTITIONING" Proc. of the
IEEE International Symposium on Circuits and Systems (ISCAS), pp. V497
 V500, 2003.

Aiman ElMaleh and Ali AlSuwaiyan, "An Efficient Test Relaxation
Technique for Combinational and FullScan Sequential Circuits" Proc. of
the 20’th IEEE VLSI Test Symposium (VTS), pp. 5359, 2002.

Aiman ElMaleh and Ali AlSuwaiyan, “An Efficient Test Relaxation
Technique for Combinational Circuits Based on Critical Path Tracing”
Proc. of the 9th IEEE International Conference on Electronics, Circuits
and Systems, pp. 461465, Sep. 2002.

Aiman ElMaleh and Raslan AlAbaji, “Extended FrequencyDirected
Run Length Code with Improved Application to Systemonachip Test Data
Compression” Proc. of the 9th IEEE International Conference on
Electronics, Circuits and Systems, pp. 449452, Sep. 2002.

Aiman ElMaleh and Ali AlSuwaiyan, “An Efficient Test Relaxation
Technique for Combinational Logic Circuits”, Proc. of the Six’th Saudi
Engineering Conference, Vol. 4, pp. 155165, Dec. 2002.

Aiman ElMaleh and Raslan AlAbaji, “On Improving the
Effectiveness of SystemonaChip Test Data Compression based on
Extended FrequencyDirected Run Length Codes” Proc. of Six’th Saudi
Engineering Conference, Vol. 4, pp. 145153, Dec. 2002.

Sadiq Sait, Aiman ElMaleh and Raslan AlAbaji, “Evolutionary
Heuristics for Multiobjective VLSI Nestlist BiPartitioning” Proc. of
Six’th Saudi Engineering Conference, Vol. 4, pp. 131143, Dec. 2002.

Aiman ElMaleh, Saif AlZahir, and Esam Khan,“A
GeometricPrimitivesBased Compression Scheme for Testing
SystemsonaChip,” 19’th IEEE VLSI Test Symposium (VTS), pp. 5459,
2001.

Aiman ElMaleh, and Yahya Osais,“A RetimingBased Test Pattern
Generator Design for BuiltIn Self Test of Data Path Architectures,”
Int. Symp. on Circuits and Systems (ISCAS), pp. 550553, 2001.

Aiman ElMaleh, Sadiq Sait, and Syed Shazli,“An Iterative
Heuristic for State Justification in Sequential Automatic Test Pattern
Generation,” 2001 Genetic and Evolutionary Computation Conference
(GECCO).

Aiman ElMaleh, Sadiq Sait, and Syed Shazli,“An Evolutionary
MetaHeuristic for State Justification in Sequential Automatic Test
Pattern Generation,” International Joint INNSIEEE Conference on Neural
Networks (IJCNN), pp. 767772, 2001.

Saif AlZahir, Aiman ElMaleh, and Esam Khan, “An Efficient Test
Vector Compression Technique Based on Geometric Shapes,” the 8th IEEE
International Conference on Electronics, Circuits and Systems (ICECS
2001), pp. 15611564, 2001.

Sadiq Sait, Habib Yousef, Aiman ElMaleh, and Mahmud Minhas,
“Iterative Heuristics for Multiobjective VLSI Standard Placement”,
International Joint INNSIEEE Conference on Neural Networks (IJCNN), pp.
22242229, 2001.

Sadiq Sait, Habib Yousef, Junaid Khan, and Aiman ElMaleh, “Fuzzy
Simulated Evolution for Low power and High Performance Optimization of
VLSI Placement”, International Joint INNSIEEE Conference on Neural
Networks (IJCNN), pp. 738743, 2001.

Sadiq Sait, Habib Yousef, Junaid Khan, and Aiman ElMaleh,
“Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI
Placement”, International Conference on Computer Design (ICCD), pp.
484487, 2001.

Aiman ElMaleh, Mark Kassab, and Janusz Rajski,“A Fast Sequential
Learning Technique for Real Sequential Circuits with Application to
Enhancing ATPG Performance,” in Proc. of 32nd Design Automation
Conference , pp. 625631, June 1998.

WuTung Cheng, Aiman ElMaleh, Rob Thompson, Don Ross, and Janusz
Rajski, “The Pitfalls of Necessary Assignments”, Fourth International
Test Synthesis Workshop, May 1997, Santa Barbara, CA.

Janusz Rajski, Aiman ElMaleh, and Jerzy Tyszer, “Arithmetic BIST
Tackles Embedded Cores,” Electronic Engineering Times, Oct. 21, 1996.

Aiman ElMaleh, Thomas Marchok, Janusz Rajski, and Wojciech Maly,
“On Test Set Preservation of Retimed Circuits,” in Proc. of the 32nd
Design Automation Conference, pp. 176182, June 1995.(Best paper award
nomination.)

Thomas Marchok, Aiman ElMaleh, Wojciech Maly, and Janusz Rajski,
“Complexity of Sequential ATPG,” in Proc. of the European Design and
Test Conference, pp. 252261, March 1995 (Winner of the best paper award
for the most outstanding contribution in the field of test in 1995).

Aiman ElMaleh and Janusz Rajski, “Algebraic Resubstitution with
Complement and Testability Preservation,” Presented at the First
International Test Synthesis Workshop, May 1994, Santa Barbara, CA.

Thomas Marchok, Aiman ElMaleh, Wojciech Maly, and Janusz Rajski,
“Test Set Preservation under Retiming Transformation,”Presented at the
First International Test Synthesis Workshop, May 1994, Santa Barbara,
CA.

Aiman ElMaleh and Janusz Rajski, “DelayFault Testability
Preservation of the Concurrent Decomposition and Factorization
Transformations,” in Proc. of IEEE VLSI Test Symposium, April 1994, pp.
1521.

Janusz Rajski, Jagadeesh Vasudevamurthy, and Aiman ElMaleh,
“Recent Advances in Logic Synthesis with Testability,” in Proc. of IEEE
VLSI Test Symposium, April 1992, pp. 254256.

Aiman H. ElMaleh, Fayez ElGuibaly, and V.K. Bhargava,
“Improving the Performance of OneDimensional Vector Quantization Using
Product Structures,” in Proc. of the 1991 First Cyprus International
Conference on Computer Applications to Engineering Systems, Nicosia,
Cyprus, July 1991, pp. 4045.

Aiman H. ElMaleh, Fayez ElGuibaly, and V.K. Bhargava, “A
Comparison of One And TwoDimensional Vector Quantization of Images,”
in Proc. of the 1991 IEEE Pacific Rim Conference on Communications,
Computers and Signal Processing, Victoria, Canada, Vol. 2, May 1991, pp.
490493.

Aiman H. ElMaleh and Sadiq M. Sait, “A State Machine Synthesizer
With Weinberger Arrays,” in Proc. of the 1991 IEEE Pacific Rim
Conference on Communications, Computers and Signal Processing, Victoria,
Canada, Vol. 2, May 1991, 753756.
Book Chapters
Aiman H. ElMaleh, Bashir M.
AlHashimi, Aissa Melouki, and Ahmad AlYamani, “TransistorLevel Based
DefectTolerance for Reliable Nanoelectronics,” pp. 2950, Robust
Computing with Nanoscale Devices: Progresses and Challenges, Chao
Huang, Springer, ISBN 9789048185399, 2010.
