Journal Publications

1)     Saleh AlSaleh, Muhammad E. S. Elrabaa, Aiman El-Maleh, Khaled Daud, Ayman Hroub, Muhamed Mudawar, Thierry Tonellot “Accelerating Memory and I/O Intensive HPC Applications Using Hardware Compressions,” Journal of Parallel and Distributed Computing, Volume 193, November 2024. [IF=3.4, Q1]

2)     Sadiq M. Sait, Aiman El-Maleh,  Mohammad Altakrouri and Ahmad Shawahna, “Optimization of FPGA-based CNN Accelerators using Metaheuristics,” Journal of Supercomputing, March. 2023. [IF=2.5, Q2]

3)     Mahmoud Habboush, Aiman H. El-Maleh, Muhammad E. S. Elrabaa and Saleh AlSaleh, “DE-ZFP: An FPGA Implementation of a Modified ZFP Compression / Decompression Algorithm,” Microprocessors and Microsystems, April 2022.  [IF=1.9, Q3]

4)     Ahmad Shawahna, Sadiq M. Sait, Aiman El-Maleh and Irfan Ahmad, “FxP-QNet: A Post-Training Quantizer for the Design of Mixed Low-Precision DNNs with Dynamic Fixed-Point Representation,” IEEE Access, March 2022. [IF=3.4, Q2]

5)     Ghashmi H. Bin Talib, Aiman El-Maleh, “Hybrid and DMR-based Fault-Tolerant Carry Look-Ahead Adder Design,” The Arabian Journal for Science and Engineering, May 2021.  [IF=2.6, Q2]

6)     Aiman El-Maleh, Saleh AlSaleh, Muhammad E. S. Elrabaa, “A Bit Addressable Register with Variable Write/Read Data widths,” The Arabian Journal for Science and Engineering, April, 2021.  [IF=2.6, Q2]

7)     Aiman H. El-Maleh, Ghashmi H. Bin Talib, “Time Redundancy and Gate Sizing Soft Error Tolerant Based Adder Design”, Integration the VLSI Journal, pp. 49-59, May 2021. [IF=2.2, Q3]

8)     Aiman El-Maleh, “A Probabilistic Tabu Search State Assignment Algorithm for Area and Power Optimization of Sequential Circuits,” The Arabian Journal for Science and Engineering, 45, pages 6273–6285, June 2020.  IF=2.6, Q2]

9)     Ahmad Shawahna, Sadiq M. Sait, and Aiman El-Maleh, “FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review,” IEEE Access, Vol. 7, Iss. 1, pp. 7823-7859, Jan. 2019. [IF=3.4, Q2]

10)   Ghashmi H. Bin Talib, Aiman H. El-Maleh, and Sadiq M. Sait, “Design of Fault Tolerant Adders: A Review,” The Arabian Journal for Science and Engineering, Volume 43, Issue 12, pp 6667–6692, December 2018.  [IF=2.6, Q2]

11)   Ahmad T. Sheikh, Aiman H. El-Maleh, "Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits," Journal of Circuits, Systems, and Computers, Volume No.27, Issue No. 6, 2018. [IF=0.9, Q4]

12)   Aiman H. El-Maleh, "A Finite State Machine Based Fault Tolerance Technique with Enhanced Area and Power of Synthesized Sequential Circuits," IET Computers & Digital Techniques,  Volume 11, Issue 4, July 2017, pp. 159 – 164. [IF=1.1, Q4]

13)   Ahmad T. Sheikh, Aiman H. El-Maleh, "An Integrated Fault Tolerance Technique for Combinational Circuits Based on Implications and Transistor Sizing," Integration, the VLSI Journal, Volume 58, June 2017, pp. 35–46. [IF=2.2, Q3]

14)   Aiman H. El-Maleh, "A Probabilistic Pairwise Swap Search State Assignment Algorithm for Sequential Circuit Optimization," Integration, the VLSI Journal, Volume 56, Jan. 2017, pp. 32–43. [IF=2.2, Q3]

15)   Ahmad T. Sheikh, Aiman H. El-Maleh, Muhammad E.S. Elrabaa, and Sadiq M. Sait, "A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy," IEEE Transactions on VLSI, Vol. 25, Iss. 1, Jan. 2017, pp. 224-237. [IF=2.8, Q2]

16)   Muhammad E. S. Elrabaa, Amran Al-Aghbari, Mohammad Al-Asli,  Aiman El-Maleh,  Abdelhafid Bouhraoua, Mohammad Alshayeb, "A low-cost Platform for the Prototyping and Characterization of Digital Circuit IPs," Integration, the VLSI Journal, Volume 54, June 2016, Pages 1–9. [IF=2.2, Q3]

17)   Aiman H. El-Maleh, "Majority-Based Evolution State Assignment Algorithm for Area and Power Optimization of Sequential Circuits," IET Computers & Digital Techniques, Vol. 10, Iss. 1, pp. 30–36, 2016. [IF=1.1, Q4]

18)   Sadiq M. Sait, Abubakar Bala, Aiman H. El-Maleh, "Cuckoo Search Based Resource Optimization of Datacenters," Applied Intelligence, April 2016, Volume 44, Issue 3, pp 489-506. [IF=3.4, Q2]

19)   Aiman H. El-Maleh and Khaled A.K. Daud, "Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits,"  IEEE Transactions on Reliability, Volume 64,  Issue 3, Sep. 2015, Pages 935 – 948. [IF=5.0, Q1]

20)   Aiman H. El-Maleh, Sadiq M. Sait, Abubakar Bala, "State Assignment for Area Minimization of Sequential Circuits Based on Cuckoo Search Optimization," Computers & Electrical Engineering, Volume 44, May 2015, Pag aes 13–23. [IF=4.0, Q1]

21)   Mohammad Alshayeb, Muhammad E. S. Elrabaa, Ayman Hroub, Amran Al-Aghbari, Aiman H. El-Maleh and Abdelhafid Bouhraoua, “Towards a Test Definition Language for Integrated Circuits,” Journal of Circuits, Systems, and Computers, Volume No.24, Issue No. 3, 2015. [IF=0.9, Q4]

22)   Aiman H. El-Maleh, Ayed S. Al-Qahtani, “A Finite State Machine Based Fault Tolerance Technique for Sequential Circuits,” Microelectronics Reliability, Volume 54, Issue 3, March 2014, Pages 491-662. [IF=1.6, Q3]

23)   Aiman H. El-Maleh, Feras Chikh Oughali, “A Generalized Modular Redundancy Scheme for Enhancing Fault Tolerance of Combinational Circuits,” Microelectronics Reliability, Volume 54, Issue 1, January 2014, Pages 316–326. [IF=1.6, Q3]

24)   Aiman H. El-Maleh, Ahmad T. Sheikh and Sadiq M. Sait, “Binary Particle Swarm Optimization (BPSO) Based State Assignment for Area Minimization of Sequential Circuits,” Applied Soft Computing, Volume 13, Issue 12, December 2013, Pages 4832–4840. [IF=7.2, Q1]

25)   Sadiq M. Sait, Ahmad T. Sheikh, Aiman H. El-Maleh, “Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm,” Journal of Applied Research and Technology, Vol. 11, October 2013, pp. 653-664. [IF=0.447, Q4]

26)   Aiman H. El-Maleh, Mohamed Adnan Landolsi and Esa A. AlGhoneim, “Window-Constrained Interconnect-Efficient Progressive Edge Growth LDPC Codes,” International Journal of Electronics and Communications, Volume 67, Issue 7, July 2013, Pages 588–594. [IF=3.0, Q2]

27)   Wenfa Zhan  and Aiman H. El-Maleh, " A New Scheme of Test Vector Compression Based on Equal-Run-Length Coding (ERLC)," Integration, the VLSI Journal, Vol. 45, pp. 91-98, 2012. [IF=2.2, Q3]

28)   Aiman El-Maleh, Saif al Zahir and Esam Khan, “Test data compression based on geometric shapes,”  Computers & Electrical Engineering, Vol. 37, Issue 3, May 2011, Pages 376-391. [IF=4.0, Q1]

29)   Esa Alghonaim, Aiman El-Maleh, M. Adnan Landolsi and Sadiq M. Sait, “A Platform for LDPC Code Design and Performance Evaluation,” The Arabian Journal for Science and Engineering, Vol. 35, No. 2B, 2010, pp. 131-148. [IF=2.6, Q2]

30)   Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman El-Maleh, “A scheme of test data compression based on coding of even bits marking and selective output inversion,” Computers and Electrical Engineering 36 (2010), pp. 969-977. [IF=4.0, Q1]

31)   Aiman El-Maleh, Bashir M. Al-Hashimi,  Aissa  Melouki and Farhan Khan, "Defect Tolerant N²-Transistor Structure for Reliable Nanoelectronic Designs," IET Computers & Digital Techniques (Special Issue on Nanoelectronics),  Vol. 3, Iss. 6, pp. 570-580, Nov. 2009. [IF=1.1, Q4]

32)   Aiman El-Maleh, Mustafa I. Ali  and Ahmad A. Al-Yamani, "Reconfigurable Broadcast Scan Compression Using Relaxation Based Test Vector Decomposition," IET Computers & Digital Techniques, Vol. 3, Iss. 2, pp. 143–161, March 2009. [IF=1.1, Q4]

33)   Esa Alghonaim, Aiman El-Maleh and Adnan Al-Andalusi, "NEW TECHNIQUE FOR IMPROVING PERFORMANCE OF LDPC CODES IN THE PRESENCE OF TRAPPING SETS," EURASIP Journal on Wireless Communications and Networking, Article ID 362897, 12 pages, 2008. doi:10.1155/2008/362897 (A special issue on Advances in Error Control Coding Techniques). [IF=2.3, Q3]

34)   Aiman El-Maleh, "Efficient Test Compression Technique Based on Block Merging," IET Comput. Digit. Tech., 2008, Vol. 2, No. 5, pp. 327–335. [IF=1.1, Q4]

35)   Aiman El-Maleh, “Test Data Compression for System-on-a-Chip using Extended Frequency-Directed Run-Length (EFDR) Code,” IET Computers & Digital Techniques, 2008, Vol. 2, No. 3, pp. 155–163. [IF=1.1, Q4]

36)   Aiman El-Maleh, Saqib Khurshid, “Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering,” IET Computers & Digital Techniques, 2007, 1, (4), pp. 364–368. [IF=1.1, Q4]

37)   Aiman El-Maleh, Saqib Khursheed, and Sadiq Sait, “Static Compaction Techniques for Sequential  Circuits Based on Reverse Order Restoration and Test Relaxation” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 11, NOVEMBER 2006, pp. 2556-2564. [IF=2.7, Q2]

38)   Sadiq M. Sait, Aiman H. El-Maleh, and Raslan H Al-Abaji, “Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning,” ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 19 (3), APR 2006, pp. 257-268.  [IF=7.5, Q1]

39)   Aiman El-Maleh, Sadiq Sait, and Syed Shazli, “Evolutionary Algorithms for State Justification in Sequential Automatic Test Pattern Generation,” ENGINEERING INTELLIGENT SYSTEMS FOR ELECTRICAL ENGINEERING AND COMMUNICATIONS 13 (1): 15-21, MAR 2005. [IF=0.091, Q4]

40)   Aiman El-Maleh and Khaled Al-Utaibi, “An Efficient Test Relaxation Technique for Synchronous Sequential Circuits,” IEEE Transactions on Computer Aided Design of Integrated Circuits, Vol. 23, No. 6, pp. 933-940, June 2004. [IF=2.7, Q2]

41)   Aiman El-Maleh and Yahya Osais, "Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits", ACM Transactions on Design Automation of Electronic Systems, Volume 8, No. 4, pp. 430-459, October 2003. [IF=2.2, Q3]

42)   Aiman El-Maleh, Thomas Marchok, Janusz Rajski, and Wojciech Maly, “Behavior and Testability Preservation Under the Retiming Transformation,” IEEE Transactions on Computer-Aided Design, Vol. 16, pp. 528-543, May 1997. [IF=2.7, Q2]

43)   Thomas Marchok, Aiman El-Maleh, Wojciech Maly, and Janusz Rajski, “A Complexity Analysis of Sequential ATPG,” IEEE Transactions on Computer-Aided Design, Vol. 15, pp. 1409-1423, Nov. 1996. IF=2.7, Q2]

44)   Aiman El-Maleh and Janusz Rajski, “Delay Fault Testability Preservation of the Concurrent Decomposition and Factorization Transformations,” IEEE Transactions on Computer-Aided Design, Vol. 14, pp. 582-590, May 1995. (A special section on 12th IEEE VLSI Test Symposium.) [IF=2.7, Q2]

45)   Thomas Marchok, Aiman El-Maleh, Janusz Rajski, and Wojciech Maly, “Testability Implications of Performance Driven Logic Synthesis,’’ in IEEE Design and Test of Computers, pp. 32-39, summer 1995.(A special issue on First International Test Synthesis Workshop.) [IF=1.623, Q3]

46)   Sadiq M. Sait and Aiman H. El-Maleh, “State Machine Synthesis with Weinberger Arrays,” Int. Journal of Electronics, Vol. 71, No. 1, pp. 1-12, July 1991. [IF=1.1, Q4]

Conference Publications

1)     A Ibrahim, A Alsultan, M Elrabaa, A El-Maleh, T Tonellot, “Efficient Implementation of Reverse Time Migration Seismic Imaging on FPGAs,” Middle East Oil, Gas and Geosciences Show, March 2023.

2)     Aiman H. El-Maleh, "A Sequential Circuit Fault Tolerance Technique with Enhanced Area and Power," 15th IEEE International Symposium on Signal Processing and Information Technology, pp. 301-304, 2015.

3)     Aiman H. El-Maleh, "State Assignment for Power Optimization of Sequential Circuits based on a Probabilistic Pairwise Swap Search Algorithm," 15th IEEE International Symposium on Signal Processing and Information Technology, pp. 305-308, 2015.

4)     Aiman H. El-Maleh, Feras Chikh Oughali, “Enhancing Reliability of Combinational Circuits against Soft Errors by Using a Generalized Modular Redundancy Scheme,” 2013 International Symposium on Electronic System Design, pp. 62-66.

5)     Wenfa Zhan  and Aiman H. El-Maleh, "A New Collaborative Scheme of Test Vector Compression Based on Equal-Run-Length Coding (ERLC)," The 13th International Conference on Computer Supported Cooperative Work in Design (CSCWD 2009), pp.21-25, April 2009.

6)     Aiman H. El-Maleh, Bashir M. Al-Hashimi and Aissa Melouki, "Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics," The sixth ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-08), Doha, Qatar, 2008 pp. 53-60.

7)     Esa Al-Ghonaim, Aiman H. El-Maleh, and Adnan Andalusi, "Using input/output queues to increase LDPC decoder performance," The sixth ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-08), Doha, Qatar, 2008, pp. 304-308.

8)     Esa Alghonaim, Aiman El-Maleh and Adnan Al-Andalusi, " PARALLEL COMPUTING PLATFORM FOR EVALUATING LDPC CODES PERFORMANCE,"   IEEE International Conference on Signal Processing and Communications (ICSPC 2007), November 2007, Dubai, United Arab Emirates, pp. 157- 160.

9)     Esa Alghonaim, Mohamed Adnan Landolsi, and Aiman El-Maleh, "IMPROVING BER PERFORMANCE OF LDPC CODES BASED ON INTERMEDIATE DECODING RESULTS,"   IEEE International Conference on Signal Processing and Communications (ICSPC 2007), November 2007, Dubai, United Arab Emirates, pp. 1547- 1550.

10)   Aiman H. El-Maleh, Mustafa Imran Ali and Ahmad A.  Al-Yamani, "A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition," 16th IEEE Asian Test Symposium, Oct. 2007. pp. 91-94.

11)   Aiman EL-MALEH, Bashir AL-HASHIMI, Ahmad AL-YAMANI, “Defect-Tolerant N²-Transistor Structure for Reliable Design at the Nanoscale,” IEEE European Test Symposium 2007, Freiburg, Germany.

12)   Aiman El-Maleh, Saqib Khurshid, “Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering,” IEEE Int. Design and Test Workshop, Nov. 19-20, UAE, 2006.

13)   Aiman El-Maleh, Basil Arkasosy, M. Adnan Al-Andalusi, “Interconnect-Efficient LDPC Code Design,” 18th IEEE Int. Conf. on Microlelectronics, Dec. 2006, Dhahran, Saudi Arabia, pp. 127-130.

14)   Aiman El-Maleh, “An Efficient Test Vector Compression Technique Based on Block Merging,” IEEE Int. Symp. on Circuits and Systems, pp. 1447-1450, May 2006.

15)   Aiman El-Maleh, Sadiq M. Sait and Faisal Nawaz Khan, “Finite State Machine State Assignment for Area and Power Minimization,” IEEE Int. Symp. on Circuits and Systems, pp. 5303-5306, May 2006.

16)   Aiman El-Maleh, Saqib Khursheed, and Sadiq Sait, “Static Compaction Techniques for Sequential  Circuits Based on Reverse Order Restoration and Test Relaxation” IEEE 14th Asian Test Symposium,  pp. 378 – 385,  Dec. 18-21 2005.

17)   Aiman El-Maleh and Yahya Osais, “A Class-based Clustering Static Compaction Technique for Combinational Circuits,” The 16th International Conference on Microelectronics, pp. 522–525, 6-8 Dec. 2004.

18)   Aiman El-Maleh and Yahya Osais, “On Test Vector Reordering for Combinational Circuits,” The 16th International Conference on Microelectronics, pp. 772 – 775, 6-8 Dec. 2004.

19)   Aiman El-Maleh, “A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip,” 10th IEEE International Conference on Electronics, Circuits and Systems, December 2003.

20)   Yahya Osais and Aiman El-Maleh, “A Static Test Compaction Technique for Combinational Circuits Based on Independent Fault Clustering,” 10th IEEE International Conference on Electronics, Circuits and Systems, December 2003.

21)   Sadiq Sait, Aiman El-Maleh and Raslan Al-Abaji, "Enhancing Performance of Iterative Heuristics for VLSI Netlist Partitioning", 10th IEEE International Conference on Electronics, Circuits and Systems, December 2003.

22)   Aiman El-Maleh and Khaled Al-Utaibi, "An Efficient Test Relaxation Technique for Synchronous Sequential Circuits" Proc. of the 21’th IEEE VLSI Test Symposium (VTS), pp. 179-185, 2003.

23)   Aiman El-Maleh and Khaled Al-Utaibi, " ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS " Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. V-545 - V-548, 2003.

24)   Sadiq Sait, Aiman El-Maleh and Raslan Al-Abaji, "SIMULATED EVOLUTION ALGORITHM FOR MULTIOBJECTIVE VLSI NETLIST BI-PARTITIONING" Proc. of the  IEEE International Symposium on Circuits and Systems (ISCAS), pp. V-457 - V-460, 2003.

25)   Sadiq Sait, Aiman El-Maleh and Raslan Al-Abaji, "GENERAL ITERATIVE HEURISTICS FOR VLSI MULTIOBJECTIVE PARTITIONING" Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. V-497 - V-500, 2003.

26)   Aiman El-Maleh and Ali Al-Suwaiyan, "An Efficient Test Relaxation Technique for Combinational and Full-Scan Sequential Circuits" Proc. of the 20’th IEEE VLSI Test Symposium (VTS), pp. 53-59, 2002.

27)   Aiman El-Maleh and Ali Al-Suwaiyan, “An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing” Proc. of the 9th IEEE International Conference on Electronics, Circuits and Systems, pp. 461-465, Sep. 2002.

28)   Aiman El-Maleh and Raslan Al-Abaji, “Extended Frequency-Directed Run Length Code with Improved Application to System-on-a-chip Test Data Compression” Proc. of the  9th IEEE International Conference on Electronics, Circuits and Systems, pp. 449-452, Sep. 2002.

29)   Aiman El-Maleh and Ali Al-Suwaiyan, “An Efficient Test Relaxation Technique for Combinational Logic  Circuits”, Proc. of the Six’th Saudi Engineering Conference, Vol. 4, pp. 155-165, Dec. 2002.

30)   Aiman El-Maleh and Raslan Al-Abaji, “On Improving the Effectiveness of System-on-a-Chip Test Data Compression based on Extended Frequency-Directed Run Length Codes” Proc. of Six’th Saudi Engineering Conference, Vol. 4, pp. 145-153, Dec. 2002.

31)   Sadiq Sait, Aiman El-Maleh and Raslan Al-Abaji, “Evolutionary Heuristics for Multiobjective VLSI Nestlist Bi-Partitioning” Proc. of  Six’th Saudi Engineering Conference, Vol. 4, pp. 131-143, Dec. 2002.

32)   Aiman El-Maleh, Saif Al-Zahir, and Esam Khan,“A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip,” 19’th IEEE VLSI Test Symposium (VTS), pp. 54-59, 2001.

33)   Aiman El-Maleh, and Yahya Osais,“A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures,” Int. Symp. on Circuits and Systems (ISCAS),  pp. 550-553, 2001.

34)   Aiman El-Maleh, Sadiq Sait, and Syed Shazli,“An Iterative Heuristic for State Justification in Sequential Automatic Test Pattern Generation,” 2001 Genetic and Evolutionary Computation Conference (GECCO).

35)   Aiman El-Maleh, Sadiq Sait, and Syed Shazli,“An Evolutionary Meta-Heuristic for State Justification in Sequential Automatic Test Pattern Generation,” International Joint INNS-IEEE Conference on Neural Networks (IJCNN), pp. 767-772, 2001.

36)   Saif Al-Zahir, Aiman El-Maleh, and Esam Khan, “An Efficient Test Vector Compression Technique Based on Geometric Shapes,” the 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2001), pp. 1561-1564, 2001.

37)   Sadiq Sait, Habib Yousef, Aiman El-Maleh, and  Mahmud Minhas, “Iterative Heuristics for Multiobjective VLSI Standard Placement”,  International Joint INNS-IEEE Conference on Neural Networks (IJCNN), pp. 2224-2229, 2001.

38)   Sadiq Sait, Habib Yousef, Junaid Khan, and Aiman El-Maleh, “Fuzzy Simulated Evolution for Low power and High Performance Optimization of VLSI Placement”, International Joint INNS-IEEE Conference on Neural Networks (IJCNN), pp. 738-743, 2001.

39)   Sadiq Sait, Habib Yousef, Junaid Khan, and Aiman El-Maleh, “Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement”, International Conference on Computer Design (ICCD), pp. 484-487, 2001.

40)   Aiman El-Maleh, Mark Kassab, and Janusz Rajski,“A Fast Sequential Learning Technique for Real Sequential Circuits with Application to Enhancing ATPG Performance,” in Proc. of 32nd Design Automation Conference , pp. 625-631, June 1998.

41)   Wu-Tung Cheng, Aiman El-Maleh, Rob Thompson, Don Ross, and Janusz Rajski, “The Pitfalls of Necessary Assignments”, Fourth International Test Synthesis Workshop, May 1997, Santa Barbara, CA.

42)   Janusz Rajski, Aiman El-Maleh, and Jerzy Tyszer, “Arithmetic BIST Tackles Embedded Cores,” Electronic Engineering Times, Oct. 21, 1996.

43)   Aiman El-Maleh, Thomas Marchok, Janusz Rajski, and Wojciech Maly, “On Test Set Preservation of Retimed Circuits,” in Proc. of the 32nd Design Automation Conference, pp. 176-182, June 1995.(Best paper award nomination.)

44)   Thomas Marchok, Aiman El-Maleh, Wojciech Maly, and Janusz Rajski, “Complexity of Sequential ATPG,” in Proc. of the European Design and Test Conference, pp. 252-261, March 1995 (Winner of the best paper award for the most outstanding contribution in the field of test in 1995).

45)   Aiman El-Maleh and Janusz Rajski, “Algebraic Resubstitution with Complement and Testability Preservation,” Presented at the First International Test Synthesis Workshop, May 1994, Santa Barbara, CA.

46)   Thomas Marchok, Aiman El-Maleh, Wojciech Maly, and Janusz Rajski, “Test Set Preservation under Retiming Transformation,”Presented at the First International Test Synthesis Workshop, May 1994, Santa Barbara, CA.

47)   Aiman El-Maleh and Janusz Rajski, “Delay-Fault Testability Preservation of the Concurrent Decomposition and Factorization Transformations,” in Proc. of IEEE VLSI Test Symposium, April 1994, pp. 15-21.

48)   Janusz Rajski, Jagadeesh Vasudevamurthy, and Aiman El-Maleh, “Recent Advances in Logic Synthesis with Testability,” in Proc. of IEEE VLSI Test Symposium, April 1992, pp. 254-256.

49)   Aiman H. El-Maleh, Fayez El-Guibaly, and V.K. Bhargava, “Improving the Performance of One-Dimensional Vector Quantization Using Product Structures,” in Proc. of the 1991 First Cyprus International Conference on Computer Applications to Engineering Systems, Nicosia, Cyprus, July 1991, pp. 40-45.

50)   Aiman H. El-Maleh, Fayez El-Guibaly, and V.K. Bhargava, “A Comparison of One- And Two-Dimensional Vector Quantization of Images,” in Proc. of the 1991 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, Canada, Vol. 2, May 1991, pp. 490-493.

51)   Aiman H. El-Maleh and Sadiq M. Sait, “A State Machine Synthesizer With Weinberger Arrays,” in Proc. of the 1991 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, Canada, Vol. 2, May 1991, 753-756.

Book Chapters

Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki, and Ahmad Al-Yamani, “Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics,” pp. 29-50, Robust Computing with Nano-scale Devices: Progresses and Challenges, Chao Huang, Springer, ISBN 978-90-481-8539-9, 2010.