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10/31/2016 coe561final_061.doc
10/31/2016 coe561final_061.pdf
10/31/2016 coe561final_081.doc
10/31/2016 coe561final_081.pdf
10/31/2016 coe561final_091.doc
10/31/2016 coe561final_101.doc
10/31/2016 coe561final_111.docx
10/31/2016 coe561finalsol_091.doc
10/31/2016 coe561finalsol_091.pdf
 3/16/2017 coe561finalsol_101.doc
10/16/2017 coe561finalsol_101.pdf
10/31/2016 coe561finalsol_111.docx
10/31/2016 coe561finalsol_111.pdf
  1/5/2019 coe561index.html
10/31/2016 coe561lectures061.doc
10/31/2016 coe561lectures061.pdf
10/31/2016 coe561lectures081.doc
10/31/2016 coe561lectures081.docx
10/31/2016 coe561lectures081.pdf
10/31/2016 coe561lectures091.docx
10/31/2016 coe561lectures091.pdf
10/31/2016 coe561lectures101.docx
10/31/2016 coe561lectures101.pdf
10/31/2016 coe561lectures111.docx
10/31/2016 coe561lectures111.pdf
10/31/2016 coe561lectures_051.doc
10/31/2016 coe561lectures_051.pdf
10/31/2016 coe561major1_061.doc
10/31/2016 coe561major1_061.pdf
10/31/2016 coe561major1_081.doc
10/31/2016 coe561major1_081.pdf
10/31/2016 coe561major1_091.doc
10/31/2016 coe561major1_091.docx
10/31/2016 coe561major1_101.docx
10/31/2016 coe561major1_111.docx
10/31/2016 coe561major1sol_091.docx
10/31/2016 coe561major1sol_091.pdf
10/31/2016 coe561major1sol_101.docx
10/31/2016 coe561major1sol_101.pdf
10/31/2016 coe561major1sol_111.docx
10/31/2016 coe561major1sol_111.pdf
10/31/2016 coe561major2_061.doc
10/31/2016 coe561major2_061.pdf
10/31/2016 coe561major2_081.doc
10/31/2016 coe561major2_081.pdf
10/31/2016 coe561major2_091.docx
10/31/2016 coe561major2_101.docx
10/31/2016 coe561major2_111.docx
10/31/2016 coe561major2sol_081.doc
10/31/2016 coe561major2sol_091.docx
10/31/2016 coe561major2sol_091.pdf
10/31/2016 coe561major2sol_101.docx
10/31/2016 coe561major2sol_101.pdf
10/31/2016 coe561major2sol_111.docx
10/31/2016 coe561major2sol_111.pdf
10/31/2016 coe561paper_eval.doc
10/31/2016 coe561paper_eval.pdf
10/31/2016 coe561presentation_eval.doc
10/31/2016 coe561presentation_eval.docx
10/31/2016 coe561presentation_eval.pdf
10/31/2016 coe561project_091.doc
10/31/2016 coe561project_091.docx
10/31/2016 coe561project_091.pdf
10/31/2016 coe561project_101.docx
10/31/2016 coe561project_101.pdf
10/31/2016 coe561project_111.docx
10/31/2016 coe561project_111.pdf
  1/5/2019 coe561syllabus.pdf
10/31/2016 coe561syllabus041.doc
10/31/2016 coe561syllabus041.pdf
10/31/2016 Coe561syllabus_051.doc
10/31/2016 Coe561syllabus_051.pdf
10/31/2016 Coe561syllabus_061.doc
10/31/2016 Coe561syllabus_061.pdf
10/31/2016 Coe561syllabus_081.doc
10/31/2016 Coe561syllabus_081.pdf
10/31/2016 Coe561syllabus_091.docx
10/31/2016 Coe561syllabus_091.pdf
10/31/2016 Coe561syllabus_101.docx
10/31/2016 Coe561syllabus_101.pdf
10/31/2016 Coe561syllabus_111.docx
10/31/2016 Coe561syllabus_111.pdf
10/31/2016 coe571hw1_072.doc
10/31/2016 coe571hw1_072.pdf
10/31/2016 covering matrices.docx
10/31/2016 Design Compiler User Guide.pdf
10/31/2016 Design Compiler.pdf
10/31/2016 Design Compiler.ppt
10/31/2016 Design_Compiler.pdf
10/31/2016 espresso.exe
10/31/2016 espresso.pdf
10/31/2016 espresso.txt
10/31/2016 ESPRESSO_TOOL_GUIDE.doc
10/31/2016 ESPRESSO_TOOL_GUIDE.pdf
10/31/2016 ex2q3_091.eqn
10/31/2016 ex2q4_091.eqn
10/31/2016 example1.eqn
10/31/2016 example1.pla
10/31/2016 example2.pla
10/31/2016 finalq5.vsd
10/31/2016 first_paper_present.pdf
 10/7/2017 How to Install Synopsys.doc
 10/7/2017 How to run Design Compiler from UNIX.pdf
10/31/2016 hw1_041.doc
10/31/2016 hw1_041.pdf
10/31/2016 hw1_051.doc
10/31/2016 hw1_051.pdf
10/31/2016 hw1_061.doc
10/31/2016 hw1_061.pdf
10/31/2016 hw1_081.doc
10/31/2016 hw1_081.pdf
10/31/2016 hw1_091.docx
10/31/2016 hw1_091.pdf
10/31/2016 hw1_101.docx
10/31/2016 hw1_101.pdf
10/31/2016 hw1_111.docx
10/31/2016 hw1_111.pdf
10/31/2016 hw1sol_051.doc
10/31/2016 hw1sol_051.pdf
10/31/2016 hw1sol_061.pdf
10/31/2016 hw1sol_081.doc
10/31/2016 hw1sol_081.pdf
10/31/2016 hw1sol_091.docx
10/31/2016 hw1sol_091.pdf
10/31/2016 hw1sol_101.pdf
10/31/2016 hw1sol_111.docx
10/31/2016 hw1sol_111.pdf
10/31/2016 hw2.pla
10/31/2016 hw2_041.doc
10/31/2016 hw2_041.pdf
10/31/2016 hw2_051.doc
10/31/2016 hw2_051.pdf
10/31/2016 hw2_061.doc
10/31/2016 hw2_061.pdf
10/31/2016 hw2_081.doc
10/31/2016 hw2_081.pdf
10/31/2016 hw2_091.doc
10/31/2016 hw2_091.docx
10/31/2016 hw2_091.pdf
10/31/2016 hw2_101.docx
10/31/2016 hw2_101.pdf
10/31/2016 hw2_111.docx
10/31/2016 hw2_111.pdf
10/31/2016 hw2_espresso.doc
10/31/2016 hw2_espresso.pdf
10/31/2016 hw2_vhdl.doc
10/31/2016 hw2_vhdl.pdf
10/31/2016 hw2q1ii.pla
10/31/2016 hw2q1ii_expand.pla
10/31/2016 hw2q1ii_irred.pla
10/31/2016 hw2q1ii_irred_input.pla
10/31/2016 hw2q1iii_irred.pla
10/31/2016 hw2q1v.pla
10/31/2016 hw2q1v_red.pla
10/31/2016 hw2q1vi.pla
10/31/2016 hw2q1vi_expand.pla
10/31/2016 hw2q2.pla
10/31/2016 hw2q2_irred.pla
10/31/2016 hw2sol_041.doc
10/31/2016 hw2sol_041.pdf
10/31/2016 hw2sol_051.pdf
10/31/2016 hw2sol_061.pdf
10/31/2016 hw2sol_091.docx
10/31/2016 hw2sol_091.pdf
10/31/2016 hw2sol_101.docx
10/31/2016 hw2sol_101.pdf
10/31/2016 hw2sol_111.docx
10/31/2016 hw2sol_111.pdf
10/31/2016 hw2sol_81.doc
10/31/2016 hw2sol_81.pdf
10/31/2016 hw2sol_espresso_041.doc
10/31/2016 hw2sol_espresso_041.pdf
10/31/2016 hw3_041.doc
10/31/2016 hw3_041.pdf
10/31/2016 hw3_051.doc
10/31/2016 hw3_051.pdf
10/31/2016 hw3_061.doc
10/31/2016 hw3_061.pdf
10/31/2016 hw3_081.doc
10/31/2016 hw3_081.pdf
10/31/2016 hw3_091.docx
10/31/2016 hw3_091.pdf
10/31/2016 hw3_101.docx
10/31/2016 hw3_101.pdf
10/31/2016 hw3_111.docx
10/31/2016 hw3_111.pdf
10/31/2016 hw3q1.eqn
10/31/2016 hw3q2.eqn
10/31/2016 hw3q3.eqn
10/31/2016 hw3sol_041.doc
10/31/2016 hw3sol_041.pdf
10/31/2016 hw3sol_051.pdf
10/31/2016 hw3sol_061.pdf
10/31/2016 hw3sol_091.docx
10/31/2016 hw3sol_091.pdf
10/31/2016 hw3sol_101.docx
10/31/2016 hw3sol_101.pdf
10/31/2016 hw3sol_111.docx
10/31/2016 hw3sol_111.pdf
10/31/2016 hw3sol_61.doc
10/31/2016 hw3sol_81.doc
10/31/2016 hw3sol_81.pdf
10/31/2016 hw3sol_sis.doc
10/31/2016 hw3sol_sis.pdf
10/31/2016 hw4.lib
10/31/2016 hw4_041.doc
10/31/2016 hw4_041.pdf
10/31/2016 hw4_051.doc
10/31/2016 hw4_051.pdf
10/31/2016 hw4_061.doc
10/31/2016 hw4_061.pdf
10/31/2016 hw4_081.doc
10/31/2016 hw4_081.pdf
10/31/2016 hw4_091.docx
10/31/2016 hw4_091.pdf
10/31/2016 hw4_101.doc
10/31/2016 hw4_101.pdf
10/31/2016 hw4_111.doc
10/31/2016 hw4_111.pdf
10/31/2016 hw4sol_041.doc
10/31/2016 hw4sol_041.pdf
10/31/2016 hw4sol_051.pdf
10/31/2016 hw4sol_061.doc
10/31/2016 hw4sol_061.pdf
 4/23/2017 hw4sol_081.doc
 4/23/2017 hw4sol_081.pdf
10/31/2016 hw4sol_091.docx
10/31/2016 hw4sol_091.pdf
10/16/2017 hw4sol_101.doc
10/16/2017 hw4sol_101.pdf
10/31/2016 hw4sol_111.doc
10/31/2016 hw4sol_111.pdf
10/31/2016 hw5_041.doc
10/31/2016 hw5_041.pdf
10/31/2016 hw5_051.doc
10/31/2016 hw5_051.pdf
10/31/2016 hw5_061.doc
10/31/2016 hw5_061.pdf
10/31/2016 hw5sol_041.doc
10/31/2016 hw5sol_041.pdf
10/31/2016 hw5sol_051.pdf
10/31/2016 hw5sol_061.doc
10/31/2016 hw5sol_061.pdf
10/31/2016 hw6_061.doc
10/31/2016 hw6_061.pdf
10/31/2016 hw6sol_061.doc
10/31/2016 hw6sol_061.pdf
10/31/2016 Introduction to VHDL.pdf
10/31/2016 Introduction to VHDL.ppt
10/31/2016 LECTURE_B_4_FSM_Encoding_intro.pptx
10/31/2016 lib2.genlib
10/31/2016 Logic Synthesis using SIS.ppt
 8/25/2018 menu561.js
10/31/2016 pla.txt
10/31/2016 Project Selection.doc
10/31/2016 Project Selection.pdf
10/31/2016 project_061.doc
10/31/2016 project_061.pdf
10/31/2016 project_081.doc
10/31/2016 project_081.pdf
10/31/2016 q1.lib
10/31/2016 q4.lib
10/31/2016 Seq_MultiplyDivide.ppt
10/31/2016 SIS Tutorial  2.pdf
10/31/2016 sis-manual.pdf
10/31/2016 sis12.exe
10/31/2016 sis_fileformats.doc
10/31/2016 sis_fileformats.pdf
10/31/2016 SIS_paper.pdf
10/31/2016 SIS_TOOL_GUIDE.doc
10/31/2016 SIS_TOOL_GUIDE.pdf
10/31/2016 State_Assignment_Thesis.pdf
10/31/2016 synch.genlib
10/31/2016 Synopsys Design Compiler Tutorial.pdf
10/31/2016 Synopsys Design Compiler Tutorial.ppt
 1/22/2019 Unit1-Introduction.pptx
10/31/2016 unit1.pdf
10/31/2016 unit1.ppt
10/31/2016 unit1.pptx
 1/22/2019 Unit2 - Combinational & Sequential Circuit Design.pptx
10/31/2016 unit2.pdf
10/31/2016 unit2.ppt
10/31/2016 unit2.pptx
 1/22/2019 Unit3-Introduction to VHDL Part I.pptx
10/31/2016 unit3.pdf
10/31/2016 unit3.ppt
10/31/2016 unit3.pptx
  1/5/2019 Unit4 - Digital System Design Based on Data Path and Control Unit.pptx
10/31/2016 unit4.pdf
10/31/2016 unit4.ppt
10/31/2016 unit4.pptx
  1/5/2019 Unit5-Introduction to VHDL - Part II.pptx
10/31/2016 unit5.pdf
10/31/2016 unit5.ppt
10/31/2016 unit5.pptx
  1/5/2019 Unit6 - Programmable Logic and Storage Devices.pptx
10/31/2016 unit6.pdf
10/31/2016 unit6.ppt
10/31/2016 unit6.pptx
  1/5/2019 Unit7 - Synthesis of Combinational Circuits.pptx
10/31/2016 unit7.pdf
10/31/2016 unit7.ppt
10/31/2016 Unit7_new.pdf
10/31/2016 Unit7_new.ppt
10/31/2016 Unit7_new.pptx
  1/5/2019 Unit8 - Architectural Synthesis.pptx
10/31/2016 unit8.pdf
10/31/2016 unit8.ppt
10/31/2016 unit9.pdf
10/31/2016 unit9.ppt
10/31/2016 using_sis.doc
10/31/2016 using_sis.pdf
10/31/2016 utiltmp
10/31/2016 Verilog Tutorial.pdf
10/31/2016 Verilog Tutorial.ppt