In this section, we will illustrate the design process of a simple CPU. Assume that the CPU has the following specifications:

	The CPU has four instructions with a fixed size format; each instruction is 8-bits long. The instructions are listed below where AX is a 6-bit register and C is a 6-bit constant. Opcode Instruction Operation 00 NOP No operation 01 LOAD C AX ← C 10 ADD C AX ← AX + C 11 SUB C AX ← AX - C
	The instruction format is as shown below: Bits 7-6 Bits 5-0 Opcode Constant
	It has one programmer accessible register, AX.
	It is a 6-bit machine with 8-bit data bus and 6-bit address bus.
	It has an adder/subtractor with two inputs: Cin: If 1 the carry-in is 1, otherwise it is 0. OP: If 0 addition is performed, otherwise subtraction is performed.

Data Path Design

The data path design for this CPU is shown below:

Fig. m300170.1 Data Path Design of the Simple CPU

The signals that control this data path are: AXout, AXin, Zout, Zin, PCout, PCin, IRout, IRin, MDRout, MARin, Cin, OP, and Select. Thus, 13 control signals are required to control the data path of this CPU. It should be observed that the 2x1 multiplexer added in the design allows passing the Adder/Subtractor B input to register Z. This is done by setting Select to 1, Cin to 0, and OP to 0 to perform addition. This also allows the implementation of an increment to the B input of the Adder/Subtractor by doing the same while setting Cin=1. Note that there is no need for the Y register due to the addition of the 2x1 multiplexer. The Z register is serving the purpose of both the Y and Z registers in the single-bus CPU design.

In addition to these signals, the control unit needs also to generate the signals Read, WMFC, and End. So, the total number of signals that need to be generated by the control unit are 16 signals.

Generation of Control Sequences

Next, we generate the step control sequences for fetching an instruction, and the four CPU instructions as shown below:

	Fetching an Instruction: T1 PCout, MARin, Select, Cin, Zin, Read T2 Zout, PCin, WMFC T3 MDRout, IRin
	NOP Instruction: T4 End
	LOAD C Instruction: T4 IRout, AXin, End
	ADD C Instruction: T4 AXout, Select, Zin T5 IRout, Zin T6 Zout, AXin, End
	SUB C Instruction: T4 AXout, Select, Zin T5 IRout, OP, Zin T6 Zout, AXin, End

Hardwired Control Unit Design for the Simple CPU

Since the maximum number of control steps is 6, the step counter size is a 3-bit counter. This requires a 3x8 step decoder. Since the opcode is 2 bits, the instruction decoder is a 2x4 decoder. The control signals equations for all the signals in the design are as follows:

	PCout = T1
	MARin = T1
	Select = T1 + T4 (ADD + SUB)
	Cin = T1
	Zin = T1 + (T4+T5) (ADD + SUB)
	Read = T1
	Zout = T2 + T6 (ADD + SUB) = T2 + T6
	PCin = T2
	WMFC = T2
	MDRout = T3
	IRin = T3
	End = T4 (NOP + LOAD) + T6 (ADD + SUB) = T4 (NOP + LOAD) + T6
	IRout = T4 LOAD + T5 (ADD + SUB) = T4 LOAD + T5
	AXin = T4 LOAD + T6 (ADD + SUB) = T4 LOAD + T6
	AXout = T4 (ADD + SUB)
	OP = T5 SUB

It should be observed that the equation for Zout has been simplified from Zout = T2 + T6 (ADD + SUB) to Zout = T2 + T6. This is because we will not reach to T6 unless the instructions are either ADD or SUB since both the NOP and LOAD instructions end at T4. Similar simplifications are done for other signals.

The hardwired control unit design for this simple CPU is shown below.

Fig. m300170.2 Hardwired Control Unit Design for the Simple CPU

Microprogrammed Control Unit Design for the Simple CPU

The first thing to specify in the microprogrammed control unit design is the control word format. For this design, due to its simplicity, we do not need branching in the microinstructions. So, there is no need for the uBranch address and the uBranch control signals.

It is also sufficient to use a 2x1 multiplexer such that one input is selected from the uPC incrementer and the other input is selected from the PLA. So, one mux select signal is needed. This design has 16 control signals to be generated. So, the number of bits in the CW is 17 bits. The format of the control word is shown below:

16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MS	PCout	MARin	Select	Cin	Zin	Read	Zout	PCin	WMFC	MDRout	IRin	End	IRout	AXin	AXout	OP

Since the number of control words in the design is 11 CWs, then the size of the control store will be 11x17 bits. Also, the size of the uPC is 4 bits. The uIR will be 17 bits; equal to the CW size. The incrementer will be a 4-bit incrementer.

The content of the control store is shown below:

Microroutine	Adress	MS	PCout	MARin	Select	Cin	Zin	Read	Zout	PCin	WMFC	MDRout	IRin	End	IRout	AXin	AXout	OP
Fetch	0000	0	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0
	0001	0	0	0	0	0	0	0	1	1	1	0	0	0	0	0	0	0
	0010	1	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0
NOP	0011	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
LOAD	0100	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	0
ADD	0101	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	1	0
	0110	0	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0
	0111	0	0	0	0	0	0	0	1	0	0	0	0	1	0	1	0	0
SUB	1000	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	1	0
	1001	0	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	1
	1010	0	0	0	0	0	0	0	1	0	0	0	0	1	0	1	0	0

Next, we need to design the PLA to provide the mapping between the opcode and the address bits. The table specifying the required mapping is shown below:

Instruction	OPC1 OPC0	PLA3 PLA2 PLA1 PLA0
NOP	00	0011
LOAD C	01	0100
ADD C	10	0101
SUB C	11	1000

Using K-map simplification, the following equations for the PLA output can be found:

	PLA0 = OPC0'
	PLA1 = OPC1' . OPC0' = (OPC1 + OPC0)'
	PLA2 = OPC1 XOR OPC0
	PLA3 = OPC1 . OPC0

The microprogrammed control unit design for this simple CPU is shown below:

Fig. m300170.3 Microprogrammed Control Unit Design for the Simple CPU