Microprogrammed Control Unit Operation 

In the microprogrammed control unit design, the control signals are generated by a program similar to machine language programs. The basic idea is that the control unit stores the values of the signals in memory instead of computing them. This can be accomplished by allocating for every signal a bit in memory, and if the signal is to be 1, the bit will store a 1; otherwise it will store a 0.

For example, suppose that the control unit needs to generate 20 control signals. Then, 20 bits are allocated for each memory address. Each memory address will store the signal values for a particular clock cycle. For example, memory address 0 will store the signal values for clock cycle T1, memory address 1 will store the signal value for clock cycle T2, and so on.

The word whose bits represent the various control signals required is called a Control Word (CD). An individual control word is also called a Microinstruction. A Microroutine is the sequence of control words corresponding to the control sequence of a machine instruction. The Control Store stores the microroutines for all instructions in the instruction set of a computer. The Control Store is a ROM since once it is programmed, it will be just read to get the signal values.

Let us consider the instruction ADD R1, [R3] (R1← R1 + [R3]) for the single-bus CPU. The control sequence for fetching this instruction and executing it using the single-bus CPU is shown in the next table:

Control Sequence Active Signals
T1 PCout, MARin, Read, ALU (C=B+1), Zin
T2 Zout, PCin, WMFC
T3 MDRout, IRin
T4 R3out, MARin, Read
T5 R1out, Yin, WMFC
T6 MDRout, ALU (C=A+B), Zin
T7 Z1out, R1in, END

We can store the required control signals for this control sequence in memory as follows:

Control Sequence Memory Address PCout MARin Read Zin Zout PCin WMFC MDRout IRin R3out R1out Yin R1in END AS1 AS0 ...
T1 0000 1111000000000001
T2 0001 00001110000000xx
T3 0002 00000001100000xx
T4 0003 01100000010000xx
T5 0004 00000010001100xx
T6 0005 0001000100000000
T7 0006 00001000000011xx

Note that for this example we assumed that the ALU can perform the following four operations: C=A+B, C=B+1, C=A-B, C=B-1. The following table shows the ALU functions and the corresponding selection lines:

ALU Function AS1 AS0

To read the control words sequentially from the control store, a Microprogram Counter (uPC) is used. The uPC is incremented every clock cycle causing successive microinstructions to be read from the control store. Thus, the control signals are delivered to the various parts of the CPU in the correct sequence.

When the instruction register (IR) is loaded with a new instruction, the address of the microroutine for the instruction to be executed is loaded into the uPC. Thus, we need an address generator that generates the address of the microroutine for each instruction based on its opcode.

The microprogrammed control unit block diagram is shown below:

Fig. m300151.1 Microprogrammed Control Unit Block Diagram

Microprogrammed Control Unit with Conditional Branching

Let us next consider the branch on Negative instruction JMPN Label (PC← Label if N=1). The microroutine for this instruction is shown in the following table:

Control Sequence Memory Address Active Signals
T1 0 PCout, MARin, Read, ALU (C=B+1), Zin
T2 1 Zout, PCin, WMFC
T3 2 MDRout, IRin, branch to starting address of appropriate routine
.............................. ............................. ................................................................................................................
T4 25 PCout, Yin, If (N=0) then branch to microinstruction 0
T5 26 (offset-field-of-IR)out, ALU (C=A+B), Zin
T6 27 Zout, PCin, END

In this example, the starting address of the microroutine for the branch on Negative instruction is 25. As can be seen from this example, in addition to generating the control signals, the control unit needs to check conditions codes or status flags to choose between alternative courses of action. Thus, additional fields are added to the microinstruction to allow the capability of conditional branching. The branch address is also added to the microinstruction.

The control unit organization to allow conditional branching in the microprogram is illustrated below:

Fig. m300151.2 Microprogrammed Control Unit to Allow Conditional Branching

In the microprogrammed control unit with conditional branching, the uPC is incremented every time a microinstruction is fetched from the microprogram memory, except in the following situations:
When a new instruction is loaded into the IR, the uPC is loaded with the starting address of the microroutine for that instruction
When an END microinstruction is encountered, the uPC is loaded with the address of the first CW in the microroutine for the instruction fetch cycle.
When a Branch microinstruction is encountered and the branch condition is satisfied, the uPC is loaded with the branch address stored in the microinstruction