Hardwired Control Unit Design 

The general hardwired control unit organization is shown below:

Fig. m300142.1 General Hardwired Control Unit Organization

It consists of a control step counter. The counter is used to keep track of the control step we are currently in. Let n be the maximum number of control steps required for implementing any instruction in the CPU. Then, the size of the control step counter is k=log2 n bits. The step counter then feeds an n x 2n Decoder to generate n control step signals T1, T2, ..., Tn. For example, if the maximum number of control steps required for implementing any instruction in the CPU n=7 (i.e. T1..T7), then K= 3 bits and the control step counter will be a 3-bit counter. The control step decoder will be a 3x8 decoder. Note that only the first 7 outputs of the decoder (corresponding to T1..T7) will be used and the last output will be ignored.

An instruction decoder is also used to decode the opcode of the instruction register to generate a signal for each instruction. For example, if the opcode is 3 bits, i.e. there are 8 instructions in the CPU, then a 3x8 instruction decoder is used to generate 8 signals, one for each instruction.

The encoder is basically the combinational logic that implements the equation for each control signal based on the control step signals, the instruction signals, and the flags.

Note here that the END signal will be connected to a synchronous reset input of the control step counter. This will ensure that when END=1 in a control step on the next rising-edge of the clock, the counter resets to 0 and hence T1 becomes 1, i.e. the control unit goes to T1 to start the fetch process fetching an instruction from memory after finishing the execution of an instruction.

Another important signal is the Run signal. This signal is ANDED with the clock to control the step counter clock. When Run=0, the clock feeding the step counter will be 0 and the counter will not increment. However, when Run=1 the counter increments on the rising-edge of the clock. The Run signal is used to control when we should wait until the memory finishes its operation and not go to the next control step. The generation of the Run signal will be illustrated when the CPU-Memory interface circuitry is discussed later.