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The execution control sequence for the JMP Label instruction for the two-bus CPU is given in the following table:
As can be seen, the number of execution control sequences for the JMP instruction is two for the two-bus CPU design while it is three in the single-bus CPU. So, there is a saving of one clock cycle in the execution of the instruction. The execution control sequence of the JMP Label instruction for the single-bus CPU is demonstrated in the next figure:
The execution control sequence for the JMPN Label instruction for the two-bus CPU is given in the following table:
Similarly, there is a saving of one clock cycle in the execution control sequence for the JMPN instruction in the two-bus CPU compared to the single-bus CPU. |