As we have seen, control signals can be generated based on the control step, the instruction being executed and Flags. For each signal, we need to find all the conditions that make the signal 1. We do that by considering all the control steps that require the signal to be 1 and derive the equation for it.

For example, let us derive the equation for the Zin signal considering only the instructions ADD R1, [R3], JMP Label, and JMPN Label for the single-bus CPU.

Zin = T1 + T6 . ADD + T5 . JMP + T5 . JMPN

As can be seen, Zin is required to become 1 in T1 in the fetch phase, in T6 of the ADD instruction, in T5 of the JMP instruction, and T5 of the JMPN instruction. The logic diagram corresponding to the equation is shown below:

Fig. m300143.1 Control Signal Generation for Zin

Similarly, the equation for the END signal can be derived as:

END = T7 . ADD + T6 . JMP + T4 . N’ . JMPN + T6 . N . JMPN
    = T7 . ADD + T6 . JMP + T4 . N’ . JMPN + T6 . JMPN

The logic diagram for the END signal is shown below:

Fig. m300143.2 Control Signal Generation for End

Similarly, the equation is derived for each signal in the design and is implemented using logic gates. This is why the approach is called hardwired since the control signals are generated by logic gates.