The execution control sequence for the JMP Label instruction for the three-bus CPU is given in the following table:

Control Sequence	Active Signals
T3	PCout, (offset-field-of-IR)out, ALU (C=A+B), PCin, END

As can be seen, the number of execution control sequences for the JMP instruction is one for the three-bus CPU design while it is two for the two-bus CPU design, and three for the single-bus CPU. So, there is a saving of one clock cycle over the two-bus CPU, and two clock cycles over the single-bus CPU in the execution of the instruction.

The execution control sequence of the JMP Label instruction for the three-bus CPU is demonstrated in the next figure:

Fig. m300138.1 Execution Control Sequence for JMP Instruction in a Three-Bus CPU

The execution control sequence for the JMPN Label instruction for the three-bus CPU is given in the following table:

Control Sequence	Active Signals
T3	PCout, (offset-field-of-IR)out, ALU (C=A+B), If (N=1) then PCin, END

Note that in the execution control sequence of this instruction, the signal PCin becomes 1 conditionally based on the sign flag (N). So, PCin becomes 1 if N=1 and we are in T3 of the JMPN instruction. If N=0, PCin will be 0 and the PC will not be loaded by the target address (Label) and the next instruction to be fetched will be the one sequentially after the JMPN instruction.

Similarly, there is a saving of one clock cycle in the execution control sequence for the JMPN instruction in the three-bus CPU compared to the two-bus CPU, and two clock cycles compared to the single-bus CPU.