Let us consider the instruction ADD R1, [R3] (R1← R1 + [R3]) and derive its execution control sequence for the three-bus CPU design. The control sequence for this instruction using the three-bus CPU is shown in the next table:

Control Sequence	Active Signals
T3	R3out,B, MARin,B, Read, WMFC
T4	MDRout, R1out,A,ALU (C=A+B), R1in, END

The execution control sequence of the ADD instruction for the three-bus CPU is demonstrated in the next figure:

Fig. m300137.1 Execution Control Sequence for ADD Instruction in a Three-Bus CPU

The number of clock cycles for the ADD instruction is 4 in the three-bus CPU, including the fetch clock cycles, while it is 7 in the single-bus CPU, and 6 in the two-bus CPU. Thus, there is a significant speedup gain in the number of clock cycles required to execute the ADD instruction.

Note that the clock period in the three-bus CPU is similar to that in the two-bus CPU as the signals propagate through the A and B buses in parallel and it requires two-bus propagation delays like the two-bus CPU.

In the next example, we will compare the execution control sequence for the instruction ADD R1, R2 for the single-bus, two-bus, and three-bus CPU designs.

Example: Generate the execution control sequence for the instruction ADD R1, R2 (R1← R1 + R2) for the single-bus, two-bus, and three-bus CPU designs.

Single-bus CPU:

T4 R1out, Yin

T5 R2out, ALU (C=A+B), Zin

T6 Zout, R1in, END

Two-bus CPU:

T4 R1out, ALU (C=B), Yin

T5 R2out, ALU (C=A+B), R1in, END

Three-bus CPU:

T3 R1out,A, R2out,B, ALU (C=A+B), R1in, END

As can be seen, the number of clock cycles to execute an instruction in the three-bus CPU design is less than those needed in the two-bus CPU design, which are less than in the single-bus CPU design.