In this section, we will illustrate the design process of a simple CPU. Assume that the CPU has the following specifications:
Data Path DesignThe data path design for this CPU is shown below:
The signals that control this data path are: AXout, AXin, Zout, Zin, PCout, PCin, IRout, IRin, MDRout, MARin, Cin, OP, and Select. Thus, 13 control signals are required to control the data path of this CPU. It should be observed that the 2x1 multiplexer added in the design allows passing the Adder/Subtractor B input to register Z. This is done by setting Select to 1, Cin to 0, and OP to 0 to perform addition. This also allows the implementation of an increment to the B input of the Adder/Subtractor by doing the same while setting Cin=1. Note that there is no need for the Y register due to the addition of the 2x1 multiplexer. The Z register is serving the purpose of both the Y and Z registers in the single-bus CPU design.
In addition to these signals, the control unit needs also to generate the signals Read, WMFC, and End. So, the total number of signals that need to be generated by the control unit are 16 signals.
Generation of Control SequencesNext, we generate the step control sequences for fetching an instruction, and the four CPU instructions as shown below:
Hardwired Control Unit Design for the Simple CPUSince the maximum number of control steps is 6, the step counter size is a 3-bit counter. This requires a 3x8 step decoder. Since the opcode is 2 bits, the instruction decoder is a 2x4 decoder. The control signals equations for all the signals in the design are as follows:
It should be observed that the equation for Zout has been simplified from Zout = T2 + T6 (ADD + SUB) to Zout = T2 + T6. This is because we will not reach to T6 unless the instructions are either ADD or SUB since both the NOP and LOAD instructions end at T4. Similar simplifications are done for other signals.
The hardwired control unit design for this simple CPU is shown below.
Microprogrammed Control Unit Design for the Simple CPUThe first thing to specify in the microprogrammed control unit design is the control word format. For this design, due to its simplicity, we do not need branching in the microinstructions. So, there is no need for the uBranch address and the uBranch control signals.
It is also sufficient to use a 2x1 multiplexer such that one input is selected from the uPC incrementer and the other input is selected from the PLA. So, one mux select signal is needed. This design has 16 control signals to be generated. So, the number of bits in the CW is 17 bits. The format of the control word is shown below:
Since the number of control words in the design is 11 CWs, then the size of the control store will be 11x17 bits. Also, the size of the uPC is 4 bits. The uIR will be 17 bits; equal to the CW size. The incrementer will be a 4-bit incrementer.
The content of the control store is shown below:
Next, we need to design the PLA to provide the mapping between the opcode and the address bits. The table specifying the required mapping is shown below:
Using K-map simplification, the following equations for the PLA output can be found:
The microprogrammed control unit design for this simple CPU is shown below: