In this section, we will discuss the microroutine for an ADD instruction with several addressing modes. The format of the ADD instruction is shown below:
ADD Rdst, Rsrc
This instruction adds the source operand to the contents of the register Rdst and places the sum in Rdst. Assume that the source operand can be specified in one of the following addressing modes:
In addition, each of these addressing modes can be either direct or indirect. In the indirect form, an additional memory read operation is performed to obtain the required operand. For example, in the register indirect addressing mode, the register contains the address of the operand. Similarly, in the Autoincrement indirect addressing mode, Rsrc contains the address of the address of the operand. So, the content of the memory address pointed by Rsrc, is the address of the operand and not the operand. So, in this case two memory reads are needed. Thus, in total the ADD instruction has 8 addressing modes for the source operand.
The instruction is assumed to be 16-bits and its format is shown below:
Bit 10 and 9 indicate the four addressing modes:
Bit 8 indicates whether the addressing mode is direct or indirect; 0=direct, 1=indirect. It is assumed that there are 16 registers in this design so 4 bits are assigned for Rsrc and 4 bits for Rdst.
The microprogram for the ADD instruction with the 8 addressing modes is shown in the following diagram. It is assumed that both the instruction and data operands are 16 bits.
Multiway BranchingAs can be seen from the microprogram for the ADD instruction with addressing modes, we need to branch to different addresses depending on the addressing mode. For example, for the addressing modes autoincrement, autodecrement and indexed, depending on whether the instruction is direct or indirect we need to branch to either address 170 or 171. This is called multiway branching.
Multiway branching for this case can be implemented in one of the following techniques:
The most efficient way for solving multiway branching is Bit Oring. The first technique increases the size of the control store as two microinstructions will be used. The second technique also increases the size of the control store as two uBranch addresses are included in each microinstruction.
With a large number of instructions with different addressing modes, generating large number of branch addresses increases circuit complexity. A simple and inexpensive way of generating the required branch addresses is to use a Programmable Logic Array (PLA). The opcode of the machine instruction is translated into the starting address of the corresponding microroutine.
Since the source operand is fetched depending on the addressing mode, this results in the need for multiway branching depending on the addressing mode. In this case, Bit Oring can also be used as an effective solution for multiway branching.
Bit OringIn this example, it is assumed that the addresses are in octal format, i.e. 3 bits per digit. The difference between the address for the direct addressing mode, 171, and the address for the indirect addressing mode, 170, is just bit 0. Thus, the microroutine will specify the address 170 and let the Bit Oring circuitry either keep Bit 0 as is or change it to 1. This is done based on Bit 8 that controls whether the addressing mode is direct or indirect.
The required addresses for fetching the source operand according to the addressing modes are shown below:
As can be observed, these addresses differ only in the middle digit. So, the address 101 can be stored in the microroutine and Bits 9 and 10 are used to change the middle digit in the address according to the addressing mode using Bit Oring.
The Bit Oring circuitry implementing multiway branching for this example is shown below:
Note that the octal address 101 is obtained from the PLA when the ADD instruction is decoded and loaded into the uPC after Oring with bits 10, 9, and 8. Bit 8 is Ored with the least significant bit going to the uPC to choose between addresses 170 and 171.
The control signal ORindrsrc is used to enable or disable Bit Oring for the case of direct and indirect addressing mode. When this signal is 0, the output of the AND gate is 0 and the address generated will be unadjusted. Similarly, the control signal ORmode is used to enable or disable Bit Oring for modifying the middle address digit. When this signal is 0, Bit Oring is disabled.
Note that the Bit Oring circuitry is placed after the 4x1 multiplexer in the design. This way, it can alter the address generated by the PLA or the uBranch address if needed.
The microroutine for the Autoincrement addressing mode for the ADD instruction using Bit Oring is shown below:
To accommodate Bit Oring for this example, two bits are added in the uBranch control signals for controlling the signals ORindrsrc and ORmode. The control store content for this example is shown below:
Note that the microroutine is not terminated by the END signal. Instead, the starting address of the fetch microroutine is specified in the uBranch address field.