Interfacing the CPU to the Memory and I/Os 

The interfacing between the CPU, the main memory and the I/Os is accomplished by mainly using two types of components; Buses and Registers.


A bus is a group of signals that interconnect several devices. They are like pathways over which information passes.

Interconnected devices use the bus on a time-share basis (i.e. each device will get a time slot to use the bus to communicate with another device).

Buses could be dedicated, i.e. connects only two devices and in this case they are called point-to-point connection.

There are three types of buses in computer systems;
  1. Data Buses that carry data
  2. Address Buses that carry addresses of memory locations or I/O devices
  3. Control Buses that carry control signals used to establish the communication sequence and protocol between the CPU , memory and peripheral devices.

Buses may be serial or parallel depending on how they carry the information:

A serial bus carries information one bit at a time,

A parallel bus carries information at several bits at a time.

One and Two-Bus Architectures

There are two major bus architectures for interconnecting the CPU to the other devices in the computer (memory and I/Os):

  1. One-Bus Architecture: in this architecture, illustrated in Fig. m010140.1, all the devices share a single bus. This bus is usually called the Backplane Bus.

    Advantages: Simplicity and ease of design.

    Disadvantages: The CPU cannot communicate with the memory and the I/Os at the same time. Also the I/Os are usually much slower than the memory, hence if there is an I/O activity, the CPU wont be able to access the memory for a long time.

    Fig. m010140.1 A Single-Bus Architecture

  2. Two-Bus Architecture: in this architecture, illustrated in Fig. m010140.2, there is a dedicated bus between the CPU and memory and another between the CPU and the I/O devices. This is more complex than the one-bus architecture but allows simultaneous memory and I/O activities, speeding up the computer operation considerably.

Fig. m010140.2 A Two-Bus Architecture

In current computers, the CPU has three-buses; one for the I/Os, one for the main memory (called the front-side bus) and another for level-two cache (called the back-side bus) to speed up the operation even further. Fig. m010140.3 illustrates a three-bus architecture.

Fig. m010140.3 A Three-Bus Architecture

An actual illustration of the Pentium bus system is shown in Fig. m010140.4.

Fig. m010140.4 The Pentium Bus Architecture

The CPU-Memory Interface

Fig. m010140.5 shows a CPU-Memory Interface using a dedicated bus architecture approach. The memory word size s is not necessary the same as the CPU’s word size w. The CPU's word size is usually referred to as the width of the data path. The following components make up the CPU-Memory interface:

  1. The Memory Address Register ( MAR ): A CPU register that holds the address of the required memory word. The size of this register determines the maximum size of the system memory. For an m-bit MAR, the maximum memory size (i.e. addressable space) is 2m words.

  2. An m-bit Address bus: It transfers the contents of the MAR to the memory.

  3. The Memory Data Register ( MDR ): A CPU register that holds the data word that is to be written to the memory or that has been fetched from the memory. Its width is equal to the data bus width, b-bits.

  4. A bi-directional b-bit Data bus: This bus transfers the data from the CPU (MDB) to the memory and vise versa. Note that b is not necessary equal to w or s. So data transfers might take more than a single cycle (if w > b) .

  5. Several control lines:

    1. R/W signal: The CPU uses this signal to specify the type of memory operation (read or write).

    2. REQUEST signal: The CPU asserts this signal to request a memory operation (while the R/W signal specifies the type of operation).

    3. Complete: The memory asserts this signal when the operation is completed.

Fig. m010140.5 CPU-Memory Interface: Signals and Registers

 Data Path, Data Bus, and Address Bus Sizes, Maximum Addressable and the Smallest Addressable Unit for Several Intel X86 Processors