COE 501 - Fall 2014
Computer Architecture

 

Muhamed F. Mudawar

mudawar@kfupm.edu.sa

Office: Building 22, Room 328, Phone: 4642

Schedule and Office Hours

Syllabus | Lectures | Assignments | Tools and Manuals

Announcements

Project Presentation: Thursday, Dec. 25, at 1 PM, Room 22/119

Final Exam: Wednesday, December 31, at 7 PM, Room 22/132

Midterm Exam: Thursday, November 13, at 6 PM, Room 22/119

Gem5 Tutorial: Tuesday, Oct 28, at 1 PM, Lab 22/129

 

Assistant

Ayman Hroub, Email: ahroub@gmail.com

Questions related to assignments and grading should be directed to the teaching assistant

Catalog Description

Computer architecture fundamentals, trends, and performance. Hardware and software approaches to ILP, dynamic speculative, VLIW, and superscalar execution models. Examples and case studies. Dynamic branch prediction techniques. Memory hierarchy, cache and virtual memory, cache coherence, memory system performance. Parallel architecture models, coherence protocols, and interconnection networks. Students are expected to carry out a research project.

Prerequisite: Graduate Standing.

Textbook

Computer Architecture, A Quantitative Approach, 5th Edition, Morgan Kaufmann Publishers, 2012.

Course Modules and Topics

  1. Defining computer architecture, classes of computers, technology trends, power in integrated circuits, cost, performance metrics, Amdahl's law, and benchmarks.

  2. Instruction set architectures, simple pipelined processors, structural, data, control hazards, data forwarding, dealing with exceptions and interrupts.

  3. Memory hierarchy design, DRAM, cache organization, multi-level caches, cache optimizations, virtual memory, cache performance.

  4. Instruction-Level Parallelism, data and control dependences, loop unrolling and compiler scheduling, branch prediction, dynamic scheduling, multiple-issue, speculation, out-of-order execution, precise exceptions, VLIW approach, limitations to ILP.

  5. Data-level parallelism, Vector architecture, vector length, vector performance, SIMD instructions for multimedia, Graphics Processing Units (GPU) architectures, memory access, detecting and enhancing loop-level parallelism.

  6. Thread-Level parallelism, multithreaded cores, multiprocessor architectures, memory models, cache coherence, and synchronization.

Academic Honesty

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Grading Components

Problem Sets : 15%

Assignments / Project : 35%

Midterm Exam : 25%

Final Exam : 25%

  

  Last Updated: Wednesday December 24, 2014, by Dr. Muhamed Mudawar