KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS

Electrical Engineering Department

EE-203 Electronics I: 2002-2003 Second Semester (022)

 

Instructor: Dr. Abdelmalek Zidouri                                           Office Location: 14-209-1

Office Hours: S M W 2:10 – 3:10 PM

Text: Microelectronic Circuits, 4th Ed. 1998, by Sedra and Smith, Oxford University Press, Inc.

 

W

Date

Sections

Topics

Lab./PSPICE

 

1

 

Feb. 22-26

 

3.1, 3.2

Diodes: Chap. 3

Ideal diode, diode characteristics.

No Lab.

2

Mar. 1-5

3.4, 3.6

Diode Models, diode applications: regulators, Zeners.

Demo # 1

Instruments

3

Mar. 8-12  

3.7, 3.8, 3.3

Diode applications: rectifiers, limiters. PN junction, physical operation of diode.

Demo # 2

Pspice

4

Mar. 15-19
 
 

4.1, 4.2, 4.3, 4.4, 4.5

Bipolar Junction Transistors (BJTs) : Chap. 4

Physical operation, types, symbols and conventions, transistors characteristics, active and saturation regions

PSPICE # 1

Diode Circuits

5

Mar. 22-26

4.6, 4.7, 4.8, 4.9

DC biasing and analysis of BJT circuits, BJT Small-signal equivalent circuit models.

Exp. # 1

Diode Applications

6

Mar. 29-Apr. 2 Exam I
Sun., Mar. 30

4.10, 4.11, 4.12

Basic single-stage BJT amplifiers: CE, CB and CC, BJT as a Switch

Exam I Sun., Mar. 30 at 5:00-6:30 in 14-108

PSPICE #3

BJT DC-Char. &

BJT Amplifiers

7

Apr. 5-9

 

4.14,13.1,

14.1, 14.2

 

BJT Logic Gates: Chap. 14

BJT logic families, TTL Inverter, digital circuit specifications, noise margins, fan-in, fan-out ,

Exp. # 2

BJT Amplifiers     

 

April 9

 

Last Day for dropping courses with grade ‘W’

8

Apr. 12 - 16

 

14.3,14.4,

14.5, 14.6

 

Other TTL circuits (NAND, NOR, …),

ECL logic circuits (e.g. NOR/OR)

TTL vs. ECL

PSPICE # 4

TTL Inverter

 

9

April 19 - 23

 

5.1, 5.2, 5.3, 5.11

Field-Effect Transistors (FETs): Chap. 5

Physical operation of  MOSFET/JFET, terminal characteristics

Exp. # 3

TTL Logic Gates

10

Apr. 26 - 30 

5.4, 5.5, 5

DC analysis of  MOSFET/JFET, small signal models

PSPICE # 5

JFET Amplifiers

 

April 30

 

Last Day for withdrawal from all courses with grade ‘W’

11

May 3 - 7

 

5.6, 5.7

FET amplifiers: CS, CG and CD amplifiers

BJT vs MOS amplifiers

Exp. # 4

FET Amplifiers

12

May 10 - 14

5.8, 5.9, 13.2, 13.3

CMOS Logic Gates: Chap. 13, 14

CMOS logic inverter, CMOS logic gates: Analysis and design, transistor sizing

PSPICE # 6

CMOS Inverter

13

May 17 - 21  

Exam II

Sun., May 18

13.5, 14.7

Pass transistor logic circuits,

BJT vs. MOS Logic: advantage/disadvantages

BiCMOS logic circuits

Exp. # 5

CMOS Logic Gates

14

May 24 - 28

 

6.1, 6.2

Differential Amplifiers: Chap. 6

BJT Differential amplifier

Exam II Sun., May. 18 at 5:00-6:30 in 14-108

Exp. # 6

Differential Amplifier

 (no prelab)

 

May 31

 

Last Day for withdrawal from all courses with grade ‘WP/WF’

15

May 31– Jun 7

6.6

MOS Differential amplifier/Review

Lab. Final

 

Grading: Attendance 2 %, HW 3%, Design 5%, Quizzes 10 %, Two Major Exams 30%, Final 30 %, Lab. 20%.

 

Absence: University Rule: 6 unexcused absences ŕ Warning; 9 unexcused absences ŕ DN