Week 
Class # 
Subject 
Ref 
Number System and Codes 

1 
1.

Introduction. Information Processing, and representation. Digital vs
Analog 
1.1 

2.

Number Systems. Binary, octal and hexadecimal numbers 
1.2, 1.3 

3. 
Number base conversion (Dec to Bin, Oct, and Hex) 
1.3 


2 
4.

Conversion between Bin, Oct, Dec, Hex. 
1.3 

5. 
Signed Binary Addition and Subtraction. R’s &(R1)’s Complement 
Handout 

6.

Codes. BCD, Excess3,
Parity Bits, ASCII & UniCodes 
1.4, 1.5 
Binary Logic & Gates 

3 
7.

Binary logic and gates, Boolean Algebra, Basic identities of Boolean
algebra. 
2.1, 2.2 

8.

Boolean functions, Algebraic manipulation, Complement of a function. 
2.2 

9.

Canonical and Standard forms, Minterms and Maxterms, Sum of products
and Products of Sums. 
2.3 
HW 1 Submitted 

4 
10.

Solution to HW 1, Map
method of simplification: Two, Three, and Fourvariable KMap 
2.4 

11.

Map method of simplification: Five, and sixvariable
KMap 
Handout 

12.

Review for Major Exam I 

Major Exam I 

5 
13.

Map manipulation: Essential
prime implicants, Nonessential prime implicants, Simplification procedure 
2.4 

14.

Don`t care conditions and
Simplification. 
2.5


15. 
Solution of Major Exam I 



6 
16.

Universal gates; NAND and
NOR gates: 2level implementation. 
2.6 

17.

Multilevel NAND Circuits 
2.6 

18.

XOR and XNOR gates, Parity
generation and checking. 
2.7 
HW 2 Submitted 

Combinational Logic 

7 
19.

Combinational Logic, Design procedure. 
3.4 

20.

Examples on combinational logic
design 
3.4 

21.

Decoders, Decoder Expansion. Combinational Circuit implementation
using decoders. 
3.5 


8 
22.

Solution to HW 2, Encoders & Priority Encoders 
3.6 

23.

Multiplexers. Function Implementation using multiplexers, Demultiplexers 
3.7 

24.

Binary Adders 
3.8 
HW 3 Submitted 

9 
25.

Solution of HW 3, Binary Subtraction 
3.9 

26.

Binary AdderSubtractors, Binary
Multipliers 
3.10, 3.11 

27.

Review for Major Exam II 

Major Exam II 

Sequential Circuits 

10 
28.

Sequential Circuits: Latches,
SR and Dlatch, Clocked latch. 
4.1,
4.2 

29.

FlipFlops: MasterSlave,
EdgeTriggered. Timing Diagrams 
4.3 

30. 
Solution for Major Exam II 



11 
31.

FlipFlops Characteristic
& Excitation Tables: DFF, SRFF,
JKFF, TFF.. 
4.3 

32.

Setup, Hold, Enable times. Timing
control and Clocks. Path delay constraints, Clock signal design. 
Handout 

33.

Sequential Circuit Design: Design
procedure, Construction of state diagrams and state tables. 
4.5 


12 
34.

Designing with DFFs. Designing
with unused states. 
4.6 

35.

Designing with JKFFs, Examples 
4.7 

36.

Sequential Circuit Analysis 
4.4

Registers & Counters 

13 
37.

Registers, Registers with
parallel load, Shift Registers. 
5.2, 5.3 

38.

Shift register with parallel
load, Bidirectional shift register. 
5.3 

39. 
Ripple Counters: UpDown Counters. 
5.4 
HW 4 Submitted 

14 
40.

Solution to HW 4, Design of Binary Counters 
5.5 

41.

Counters with DFF. Serial and Parallel Counter, UpDown Binary Counter

5.5


42.

Binary Counter with Parallel
Load, Other Counters 
5.5, 5.6 
Memory & PLDs 

15 
43.

Memory and Programmable
Logic Devices: Random Access Memory. 
6.1, 6.2 

44.

Combinational
Circuit Implementation with 
6.6 

45.

Programmable logic Array, Programmable
Array logic devices and FPGAs 
6.8, 6.9 