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Week |
Class # |
Subject |
Ref |
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Number System and Codes |
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1 |
1.
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Introduction. Information Processing, and representation. Digital vs
Analog |
1.1 |
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2.
|
Number Systems. Binary, octal and hexadecimal numbers |
1.2, 1.3 |
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|
3. |
Number base conversion (Dec to Bin, Oct, and Hex) |
1.3 |
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2 |
4.
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Conversion between Bin, Oct, Dec, Hex. |
1.3 |
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5. |
Signed Binary Addition and Subtraction. R’s &(R-1)’s Complement |
Handout |
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6.
|
Codes. BCD, Excess-3,
Parity Bits, ASCII & Uni-Codes |
1.4, 1.5 |
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Binary Logic & Gates |
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3 |
7.
|
Binary logic and gates, Boolean Algebra, Basic identities of Boolean
algebra. |
2.1, 2.2 |
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8.
|
Boolean functions, Algebraic manipulation, Complement of a function. |
2.2 |
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9.
|
Canonical and Standard forms, Minterms and Maxterms, Sum of products
and Products of Sums. |
2.3 |
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HW 1 Submitted |
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|
4 |
10.
|
Solution to HW 1, Map
method of simplification: Two-, Three-, and Four-variable K-Map |
2.4 |
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11.
|
Map method of simplification: Five, and six-variable
K-Map |
Handout |
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12.
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Review for Major Exam I |
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|
Major Exam I |
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|
5 |
13.
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Map manipulation: Essential
prime implicants, Nonessential prime implicants, Simplification procedure |
2.4 |
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14.
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Don`t care conditions and
Simplification. |
2.5
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15. |
Solution of Major Exam I |
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|
6 |
16.
|
Universal gates; NAND and
NOR gates: 2-level implementation. |
2.6 |
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17.
|
Multilevel NAND Circuits |
2.6 |
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18.
|
XOR and XNOR gates, Parity
generation and checking. |
2.7 |
|
HW 2 Submitted |
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Combinational Logic |
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|
7 |
19.
|
Combinational Logic, Design procedure. |
3.4 |
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20.
|
Examples on combinational logic
design |
3.4 |
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21.
|
Decoders, Decoder Expansion. Combinational Circuit implementation
using decoders. |
3.5 |
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|
8 |
22.
|
Solution to HW 2, Encoders & Priority Encoders |
3.6 |
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23.
|
Multiplexers. Function Implementation using multiplexers, Demultiplexers |
3.7 |
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24.
|
Binary Adders |
3.8 |
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HW 3 Submitted |
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|
9 |
25.
|
Solution of HW 3, Binary Subtraction |
3.9 |
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26.
|
Binary Adder-Subtractors, Binary
Multipliers |
3.10, 3.11 |
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27.
|
Review for Major Exam II |
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Major Exam II |
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Sequential Circuits |
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|
10 |
28.
|
Sequential Circuits: Latches,
SR and D-latch, Clocked latch. |
4.1,
4.2 |
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29.
|
Flip-Flops: Master-Slave,
Edge-Triggered. Timing Diagrams |
4.3 |
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30. |
Solution for Major Exam II |
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|
11 |
31.
|
Flip-Flops Characteristic
& Excitation Tables: D-FF, SR-FF,
JK-FF, T-FF.. |
4.3 |
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32.
|
Setup, Hold, Enable times. Timing
control and Clocks. Path delay constraints, Clock signal design. |
Handout |
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33.
|
Sequential Circuit Design: Design
procedure, Construction of state diagrams and state tables. |
4.5 |
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|
12 |
34.
|
Designing with D-FFs. Designing
with unused states. |
4.6 |
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35.
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Designing with JK-FFs, Examples |
4.7 |
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36.
|
Sequential Circuit Analysis |
4.4
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Registers & Counters |
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|
13 |
37.
|
Registers, Registers with
parallel load, Shift Registers. |
5.2, 5.3 |
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38.
|
Shift register with parallel
load, Bi-directional shift register. |
5.3 |
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39. |
Ripple Counters: Up-Down Counters. |
5.4 |
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HW 4 Submitted |
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|
14 |
40.
|
Solution to HW 4, Design of Binary Counters |
5.5 |
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41.
|
Counters with D-FF. Serial and Parallel Counter, Up-Down Binary Counter
|
5.5
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42.
|
Binary Counter with Parallel
Load, Other Counters |
5.5, 5.6 |
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Memory & PLDs |
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|
15 |
43.
|
Memory and Programmable
Logic Devices: Random Access Memory. |
6.1, 6.2 |
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44.
|
Combinational
Circuit Implementation with |
6.6 |
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45.
|
Programmable logic Array, Programmable
Array logic devices and FPGAs |
6.8, 6.9 |