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Muhamed F. Mudawar
mudawar@kfupm.edu.sa
Office: Building 22, Room 328, Phone: 4642
Office Hours: SMW 12 noon - 1 pm
Syllabus |
Lectures |
Assignments |
Tools and Manuals |
Fall 2007
Announcements
Final Exam: Wednesday, June 24, 7:30 AM, Building 24, Room 106
Quiz 4 on Floating-Point Arithmetic: Saturday, May 23
Quiz 3 on Performance and Metrics: Saturday, May 16
Major Exam 1: Sunday, April 12, 7 PM, Building 24, Room 120
Covers: Introduction, MIPS Instruction Set Architecture & Assembly
Language
Quiz 2 on MIPS Instruction and Assembly Language:
Monday, March 30
Quiz 1 on Intro Computer Architecture:
Saturday, March 14
Assistant
Abdullah Al-Amoudi
Email:
a_a_ba@hotmail.com
Questions related to
assignments and grading should be directed to the teaching assistant
Textbooks
David A. Patterson and John L. Hennessy, Computer Organization &
Design, The Hardware/Software Interface,
Third Edition, Morgan Kaufmann Publishers, 2005. ISBN: 1-55860-604-1.
Robert L. Britton, MIPS
Assembly Language Programming, Pearson Prentice Hall, 2004.
Course Objectives
Towards the end of this course,
students should be able to:
Describe the instruction set
architecture of a MIPS processor
Analyze, write, and test MIPS
assembly language programs
Describe the
organization/operation of integer and floating-point arithmetic units
Design the datapath and control
of a single-cycle processor
Design the datapath and control
of a pipelined processor and handle hazards
Describe the
organization/operation of memory and caches
Analyze the performance of
processors and caches
Academic Honesty
View
important information on academic honesty
Exam
Schedule
Exam 1: Sunday, April 12, 7
PM, Building 24, Room 120
Exam 2: Tuesday, May 26, 7
PM, Building 24, Room 121
Final Exam: Wednesday, June
24, 7:30 AM, Building 24, Room 106
Sample Exams
Exam 1
- Fall 2007
Exam-2 - Fall 2007
Final Exam - Fall 2007
Grading
Lab work: 15%
Homeworks and Quizzes:
10%
Programming Assignments: 15%
Project: 10%
Midterm Exam I: 15%
Midterm Exam II: 15%
Final
Exam: 20%
Course
Topics
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Week |
Course Topics |
Reading |
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1 |
Introduction to computer
architecture, ISA versus organization, high-level, assembly, and
machine languages, components of a computer system, abstraction,
technology improvements, chip manufacturing process. |
Chapter 1 |
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2 |
Instruction set design,
RISC design principles, MIPS registers, instruction formats,
arithmetic instructions, immediate operands, bit manipulation,
load and store instructions, byte ordering, addressing modes,
flow control instructions, pseudo-instructions, MIPS
register conventions. |
Sections 2.1 – 2.9
Sections 2.13, 2.15 – 2.18
Sections 3.2 – 3.3
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3 |
MIPS assembly language programming, tools, program template,
directives, text, data, and stack segments, defining data,
arrays, and strings, array indexing and traversal, translating
expressions, if-else statements, loops, indirect jump, console
input and output |
Appendix A |
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4 |
Runtime stack and its applications, defining procedures,
procedure calls and return address, nested procedure calls,
passing arguments in registers and on the stack, stack frames,
value and reference parameters, saving and restoring registers,
local variables on the stack |
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6 , 7 |
Review of data representation, binary and hexadecimal
addition and subtraction, carry and overflow, characters and the
ASCII table. Integer multiplication,
integer division, floating point representation, IEEE 754
standard, normalized and de-normalized numbers, zero, infinity, NaN, FP comparison, FP addition, FP multiplication, rounding and
accurate arithmetic, FP instructions in MIPS. |
Sections 3.2 – 3.3
Sections 3.4 – 3.6
Sections 3.8 – 3.9 |
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8 |
CPU performance and
metrics, CPI, performance equation, MIPS as a metric, Amdahl’s
law, benchmarks and performance of recent Intel processors. |
Chapter 4 |
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9 , 10 |
Designing a processor,
register transfer logic, datapath components, clocking
methodology, single-cycle datapath, main control signals, ALU
control, single-cycle delay, multi-cycle instruction execution,
multi-cycle implementation, CPI in a multi-cycle CPU. |
Sections 5.1 – 5.5 |
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11 |
Pipelining versus serial
execution, MIPS 5-stage pipeline, pipelined datapath, pipelined
control, pipeline performance. |
Sections 6.1 – 6.3 |
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12 |
Pipeline hazards,
structural hazards, data hazards, stalling pipeline, forwarding,
load delay, compiler scheduling, hazard detection, stall and
forwarding unit, control hazards, branch delay, dynamic branch
prediction, branch target and prediction buffer.
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Sections 6.4 – 6.6 |
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13 , 14 |
Cache memory design,
locality of reference, memory hierarchy, DRAM and SRAM,
direct-mapped, fully-associative, and set-associative caches,
handling cache miss, write policy, write buffer, replacement
policy, cache performance, CPI with memory stall cycles, AMAT,
two-level caches and their performance, main memory organization
and performance. |
Sections 7.1 – 7.3
Sections 7.5 – 7.6 |
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