ICS 233 Computer Architecture and Assembly Language

Week	Course Topics	Reading
1	Introduction to computer architecture, ISA versus organization, high-level, assembly, and machine languages, components of a computer system, abstraction, technology improvements, chip manufacturing process.	Chapter 1
2	Instruction set design, RISC design principles, MIPS registers, instruction formats, arithmetic instructions, immediate operands, bit manipulation, load and store instructions, byte ordering, addressing modes, flow control instructions, pseudo-instructions, MIPS register conventions.	Sections 2.1 – 2.9 Sections 2.13, 2.15 – 2.18 Sections 3.2 – 3.3
3	MIPS assembly language programming, tools, program template, directives, text, data, and stack segments, defining data, arrays, and strings, array indexing and traversal, translating expressions, if-else statements, loops, indirect jump, console input and output	Appendix A
4	Runtime stack and its applications, defining procedures, procedure calls and return address, nested procedure calls, passing arguments in registers and on the stack, stack frames, value and reference parameters, saving and restoring registers, local variables on the stack
6 , 7	Review of data representation, binary and hexadecimal addition and subtraction, carry and overflow, characters and the ASCII table. Integer multiplication, integer division, floating point representation, IEEE 754 standard, normalized and de-normalized numbers, zero, infinity, NaN, FP comparison, FP addition, FP multiplication, rounding and accurate arithmetic, FP instructions in MIPS.	Sections 3.2 – 3.3 Sections 3.4 – 3.6 Sections 3.8 – 3.9
8	CPU performance and metrics, CPI, performance equation, MIPS as a metric, Amdahl’s law, benchmarks and performance of recent Intel processors.	Chapter 4
9 , 10	Designing a processor, register transfer logic, datapath components, clocking methodology, single-cycle datapath, main control signals, ALU control, single-cycle delay, multi-cycle instruction execution, multi-cycle implementation, CPI in a multi-cycle CPU.	Sections 5.1 – 5.5
11	Pipelining versus serial execution, MIPS 5-stage pipeline, pipelined datapath, pipelined control, pipeline performance.	Sections 6.1 – 6.3
12	Pipeline hazards, structural hazards, data hazards, stalling pipeline, forwarding, load delay, compiler scheduling, hazard detection, stall and forwarding unit, control hazards, branch delay, dynamic branch prediction, branch target and prediction buffer.	Sections 6.4 – 6.6
13 , 14	Cache memory design, locality of reference, memory hierarchy, DRAM and SRAM, direct-mapped, fully-associative, and set-associative caches, handling cache miss, write policy, write buffer, replacement policy, cache performance, CPI with memory stall cycles, AMAT, two-level caches and their performance, main memory organization and performance.	Sections 7.1 – 7.3 Sections 7.5 – 7.6

Last Updated: Saturday September 01, 2012, by Dr. Muhamed Mudawar