King Fahd University of Petroleum & Minerals
College of Computer Sciences and Engineering

Computer Engineering Department
COE 301 Computer Organization
Course Syllabus

Course Objectives:

  1. Ability to apply knowledge of mathematics, probability, and statistics in computer analysis and design,

  2. Ability to design the datapath and control of a processor,

  3. Ability to identify, formulate, and solve computer architecture problems,

  4. Ability to engage in self-learning, and

  5. Ability to use simulator tools.

Catalog Description
Instruction set architecture, CPU performance and metrics, Integer and floating-point arithmetic, datapath and control design, instruction pipelining, pipeline hazard detection and resolution, memory hierarchy, cache organization, virtual memory, I/O subsystem, and multiprocessors.
Prerequisite: COE 205.


7.      Introduction and Performance (5 Lectures)
Introduction to computer architecture, ISA versus organization, components, abstraction, technology improvements, chip manufacturing process (Chapter 1).  CPU performance and metrics, CPI, performance equation, MIPS as a metric, Amdahl’s law, and benchmarks and performance of recent Intel processors. (Chapter 4).

8.      Instructions: the language of the machine. (3 Lectures)
Computer hardware, instruction representation, making decisions, procedures, addressing modes, and MIPS instruction set. (Selected material from Sections 2.1 – 2.9, 2.13, and 2.15 – 2.18)

9.      Computer Arithmetic. (6 Lectures)
Integer multiplication, integer division, floating point representation, IEEE 754 standard, normalized and de-normalized numbers, zero, infinity, NaN, FP comparison, FP addition, FP multiplication, rounding and accurate arithmetic, FP instructions in MIPS (Sections 3.4-3.6 and 3.8-3.9)

10.  Datapath and Control (6 Lectures)
Designing a processor, register transfer logic, datapath components, clocking methodology, single-cycle datapath, main control signals, ALU control, single-cycle delay, multi-cycle instruction execution, multi-cycle implementation, CPI in a multi-cycle CPU. (Sections 5.1 – 5.5)

11.  Enhancing performance with pipelining (9 Lectures)
Pipelining versus serial execution, MIPS 5-stage pipeline, pipelined datapath, pipelined control, pipeline performance. Pipeline hazards, structural hazards, data hazards, stalling pipeline, forwarding, load delay, compiler scheduling, hazard detection, stall and forwarding unit, control hazards, branch delay, dynamic branch prediction, branch target and prediction buffer. Advanced pipelining.  (Sections 6.1 – 6.6 and 6.9)

12.  Memory System Design (8 Lectures)
 Cache memory design, locality of reference, memory hierarchy, DRAM and SRAM, direct-mapped, fully-associative, and set-associative caches, handling cache miss, write policy, write buffer, replacement policy, cache performance, CPI with memory stall cycles, AMAT, two-level caches and their performance, main memory organization and performance. Virtual memory, address mapping, page table, handling a page fault, TLB, virtual versus physical caches, overlapped TLB and cache access. (Sections 7.1 – 7.3, 7.4, and 7.5 – 7.6)

13.  I/O and Buses (2 Lectures)
I/O subsystem and devices, disk operation, dependability, reliability and availability, RAID, busses, bus operation, I/O performance. (Sections 8.1, 8.2 and 8.6)

14.  Multiprocessors (4 Lectures)
Programming multiprocessors, and multiprocessors connected by a single bus and by a network. clusters, network topologies, chip multiprocessors, multithreading, example of cluster PCs. (Sections 9.1-9.8).

Computer Usage: Programming assignments may be required to simulate various components of a computer like a pipeline, cache memory, or a multiprocessor.

Course Outcomes



Course Learning



Outcome Indicators and Details


O1. Ability to apply knowledge of mathematics, probability, and statistics in computer analysis and design.

·        Integer representation, addition, and multiplication

·        Floating-point representation, rounding, normalization, addition, and multiplication.

·        Program and instruction execution times and stall cycles.

·        Speedup computation

·        Evaluation of the average performance of I-pipelining and memory system

O2. Ability to design the datapath and control of a processor.


·        Design generic datapath based on Instruction Set requirements.

·        Identify datapath components and clocking methodology.

·        Design a detailed single-cycle integer datapath, Muxes, and PC updating.

·        Identify control signals and design control logic

·        Design inter-stage buffers and clocking for multicycle datapath.

·        Design multi-cycle control states and logic.

·        Design pipelined datapath and control

·        Detect and eliminate structural hazards

·        Detect data hazards and implement forwarding

·        Handle control hazards and predict branches


O3. Ability to identify, formulate, and solve computer architecture problems.


·        Assess design methodologies in single-cycle, multi-cycle, and multiple-issue datapaths.

·        Assess tradeoffs in cache design, page size, bus width, degree of associativity, cache capacity, and main memory access time. 

·        Assess tradeoffs in address translation, virtual page size, TLB size, sequential versus concurrent TLB and cache access.

·        Assess scalability issues in shared-memory and distributed-memory systems.

O4. Ability to use simulator tools.




·        Ability to set up a simulator.

·        Set up simulation runs based on some design specifications.

·        Run simulations and collect results and statistics

·        Ability to analyze simulation results and modify design specifications to improve performance.

O5. Ability to engage in self-learning.


·         Demonstrates reading, writing, listening and speaking skills

·         Identifying, retrieving, and organizing information

·         Following a learning plan

·         Demonstrate critical thinking skills such as applying the facts, formulas, theories, etc. to everyday situations.


Working Groups:
The instructor encourages the students to work in groups for reviewing the class lectures, preparation for exams, and discussion (only) of homework problems. Participants receive bonus grades for such activities. The organization of these groups is as follows. Any student with a GPA above 3.0 can be considered as a class leader. Each class leader is encouraged to create a Working Group of 3 or 4 students to review the course material of COE 308. A Bonus will be given to all members of a Working Group for each meeting of the group. Students with a GPA above 3.0 wishing to participate in this activity are pleased to give their name and ID to the instructor. Students wishing to participate as group members may ask the instructor about the class leaders and their groups. The class leader has the responsibility of providing the instructor the list of students who attended a meeting. This list should include the students name, date of meeting, and signatures. Any student can attend the lecture review meetings with any of the Class Leaders.


Study of the PCSpim processor simulator which runs MIPS R2000/R3000 assembly language programs. The students may read the Appendix A in Patterson and Hennessy book to be familiar with the environment. Please see presentations and material at URL:

The student uses the Logisim version 2.1.4 design tool (see Website for Logisim) for the design of a Single-Cycle Processor Design which can be extended to a Pipelined Processor. See above link for more information.