King Fahd University of Petroleum & Minerals
College of Computer Sciences and Engineering

Computer Engineering Department
COE 202 Digital Logic Design
Course Syllabus

• Instructor: Professor Mayez Al-Mouhamed
• Office: 22-400-3, office phone 2934, lab phone 3536.
• Office hours: From 10 to 11 am on S.M.W and from 11 to 12 am on S.T.  and by appointment in the case of time conflict.
• Grading: Exam 1: 15/100, Exam 2: 15/100, Three Quiz (15/100), Homework (4) 10/100, and Final Exam: 30/100
• Exams: Exam 1: 20/100 (Saturday, November 8, 2008), Exam 2: 25/100 (Saturday, December 27, 2008), Quiz1-2-3: 15/100  (Q1: Saturday, Oct. 25, Q2: Saturday Nov. 15, and Q3: Saturday Jan. 10, 2009), Homework (4): 10/100, and Final Exam: 30/100 (scheduled by the registrar).
• Text Book and references:
• Text Book: M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall International, 2002.
• Course Material: See below.
• Attendance: attendance is required by all students. Excuse for official authorized must be presented to the instructor no later than one week following the absence. unexcused absences may lead to a ``DEN'' grade.

Course Objectives:

• Carry out arithmetic computations in various number systems (Binary, Octal, Hexadecimal).

• Apply rules of Boolean algebra to simplify Boolean expressions.

• Translate Boolean expressions into equivalent truth tables and logic gate implementations and vice versa.

• Design efficient combinational and sequential logic circuit implementations from functional description of digital systems.

• Carry out simple CAD simulations to verify the operation of logic circuit

Catalog Description
Introduction to Computer Engineering. Digital Circuits. Boolean algebra and switching theory. Manipulation and minimization of Boolean functions. Combinational circuits analysis and design, multiplexers, decoders and adders. Sequential circuit analysis and design, basic flip-flops, clocking and edge-triggering, registers, counters, timing sequences, state assignment and reduction techniques. Register transfer level operations. (Prerequisite: PHYS 102)

COURSE TOPICS

·         Number System and Codes: Information Processing, and representation. Digital vs Analog quantities. General Number Systems. Binary, Octal and Hexadecimal systems. Number System Arithmetic (Addition, Subtraction & Multiplication). Number base conversion. Binary Storage & Registers. Signed Binary Number representation (Signed Mag, R’s &(R-1)’s Complement). Signed Binary Addition and Subtraction ((R-1)’s, R’s Complement Addition and Subtraction). Codes.  BCD, Excess-3, Parity Bits, ASCII & Unicode.

·         Binary Logic & Gates: Boolean Algebra; basic identities, algebraic manipulation, complement of a function. Canonical and Standard forms, minterms and Maxterms, Sum of products and Products of Sums. Physical properties of gates: fan-in, fan-out, propagation delay, timing diagrams and Tri-state drivers. Map method of simplification: Two-, Three-, Four-and Five-variable K-Maps. Essential prime implicants, simplification procedure, SOP & POS simplification, Don’t care conditions. Universal gates; NAND, NOR gates: 2-level implementations. Multilevel Circuits. Exclusive-OR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation and checking.

·         Combinational Logic: Design Procedure & Examples. Half and Full Adders, Binary Adders: 4-Bit Ripple Carry Adder and delay analysis. Carry Look-Ahead Adder, Adder-Subtractor circuit. MSI parts. Decoders, Decoder expansion,  combinational logic implementation using decoders, Encoders & Priority Encoders, Multiplexers, Function Implementation using multiplexers, Demultiplexers, Magnitude Comparator. Design Examples.

·         Sequential Circuits: Latches, Clocked latches: SR, D, T and JK. Race problem in clocked JK-Latch. Function & Excitation Tables of clocked latches: SR, D, T and JK. Flip-Flops: Master-Slave, and edge-triggered. Function & Excitation Tables of T-FF. Asynchronous/Direct Clear and Set Inputs. Setup &Hold times. Sequential Circuit Design: Excitation Tables. Design procedure, State diagrams and state tables. Sequential Circuit Analysis: Input equations, State table. Mealy vs. Moore models of FSMs. Examples. Registers and counters.

·         Memory & PLDs: Memory devices: RAMs & ROMs . Combinational Circuit Implementation with ROM. Programmable Logic Devices: PLAs, PALs, and FPGA’a

MEETING THE PROFESSIONAL COMPONENTS

This course emphasizes the design and analysis of combinational as well as sequential digital logic circuits. For this end, the course also emphasizes the ability of students to use Boolean algebra to simplify functions using both the algebraic and the K-map techniques.

COURSE OUTCOMES