King Fahd University of Petroleum & Minerals
College of Computer Sciences and Engineering
Computer Engineering Department
COE 202 Digital Logic Design
Course Syllabus
Course Objectives:
Carry out arithmetic computations in various number systems (Binary, Octal, Hexadecimal).
Apply rules of Boolean algebra to simplify Boolean expressions.
Translate Boolean expressions into equivalent truth tables and logic gate implementations and vice versa.
Design efficient combinational and sequential logic circuit implementations from functional description of digital systems.
Carry out simple CAD simulations to verify the operation of logic circuit
Catalog Description
Introduction to Computer Engineering. Digital Circuits. Boolean algebra and
switching theory. Manipulation and minimization of Boolean functions.
Combinational circuits analysis and design, multiplexers, decoders and
adders. Sequential circuit analysis and design, basic flipflops, clocking
and edgetriggering, registers, counters, timing sequences, state assignment
and reduction techniques. Register transfer level operations. (Prerequisite:
PHYS 102)
COURSE TOPICS
· Number System and Codes: Information Processing, and representation. Digital vs Analog quantities. General Number Systems. Binary, Octal and Hexadecimal systems. Number System Arithmetic (Addition, Subtraction & Multiplication). Number base conversion. Binary Storage & Registers. Signed Binary Number representation (Signed Mag, R’s &(R1)’s Complement). Signed Binary Addition and Subtraction ((R1)’s, R’s Complement Addition and Subtraction). Codes. BCD, Excess3, Parity Bits, ASCII & Unicode.
· Binary Logic & Gates: Boolean Algebra; basic identities, algebraic manipulation, complement of a function. Canonical and Standard forms, minterms and Maxterms, Sum of products and Products of Sums. Physical properties of gates: fanin, fanout, propagation delay, timing diagrams and Tristate drivers. Map method of simplification: Two, Three, Fourand Fivevariable KMaps. Essential prime implicants, simplification procedure, SOP & POS simplification, Don’t care conditions. Universal gates; NAND, NOR gates: 2level implementations. Multilevel Circuits. ExclusiveOR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation and checking.
· Combinational Logic: Design Procedure & Examples. Half and Full Adders, Binary Adders: 4Bit Ripple Carry Adder and delay analysis. Carry LookAhead Adder, AdderSubtractor circuit. MSI parts. Decoders, Decoder expansion, combinational logic implementation using decoders, Encoders & Priority Encoders, Multiplexers, Function Implementation using multiplexers, Demultiplexers, Magnitude Comparator. Design Examples.
· Sequential Circuits: Latches, Clocked latches: SR, D, T and JK. Race problem in clocked JKLatch. Function & Excitation Tables of clocked latches: SR, D, T and JK. FlipFlops: MasterSlave, and edgetriggered. Function & Excitation Tables of TFF. Asynchronous/Direct Clear and Set Inputs. Setup &Hold times. Sequential Circuit Design: Excitation Tables. Design procedure, State diagrams and state tables. Sequential Circuit Analysis: Input equations, State table. Mealy vs. Moore models of FSMs. Examples. Registers and counters.
· Memory & PLDs: Memory devices: RAMs & ROMs . Combinational Circuit Implementation with ROM. Programmable Logic Devices: PLAs, PALs, and FPGA’a
MEETING THE PROFESSIONAL COMPONENTS
This course emphasizes the design and analysis of combinational as well as sequential digital logic circuits. For this end, the course also emphasizes the ability of students to use Boolean algebra to simplify functions using both the algebraic and the Kmap techniques.
COURSE OUTCOMES
Course Learning Outcomes 
Outcome Indicators and Details 
O1. Ability to apply math and Boolean algebra in performing computations in various number systems and simplification of Boolean algebraic expressions. [ABET Criterion 3a] 
· Digital vs Analog quantities. · General Number Systems. Binary, Octal and Hexadecimal systems. Number System Arithmetic (Addition, Subtraction & Multiplication). · Number base conversion. Binary Storage & Registers. Signed Binary Number representation (Signed Mag, R’s &(R1)’s Complement). · Signed Binary Addition and Subtraction ((R1)’s, R’s Complement Addition and Subtraction). Codes. BCD, Excess3, Parity Bits, ASCII & Unicode. · Represent integer and fractional values in various number systems · Convert number representation from one system to another · Perform arithmetic operations in various number systems · Represent data in different binary codes including error detecting codes Simplify Boolean expressions using Boolean algebra & identities

O2. Ability to design efficient combinational and sequential logic circuit implementations from functional description of digital systems. [ABET Criterion 3c] 
Moore & Mealy models from functional description

O3. Ability to use CAD tools to simulate and verify logic circuits. [ABET Criterion 3k] 

Working Groups:
The instructor encourages the students to work in groups for reviewing the
class lectures, preparation for exams, and discussion (only) of homework
problems. Participants receive bonus grades for such activities. A Bonus will be given to all members of a Working Group
for each meeting of the group. Students wishing to participate as
group members may ask the instructor about the class leaders and their
groups. A group leader has the responsibility of providing the instructor
the list of students who attended a meeting. This list should include the
students name, date of meeting, and signatures. Any student can attend the
lecture review meetings.