TEACHING MATERIAL

TOPICS BREAKDOWN

•  Unit I Number System and Codes PDF 1 Introduction. Information Processing, and representation. Digital vs Analog quantities. 2 Number Systems. Binary, Octal and Hexadecimal #’s 3 Number System Arithmetic. Binary arith (Addition, Subtraction & Multiplication). Arith in other systems. 4 Number base conversion (Dec to Bin, Oct, and Hex, General). Conv (Bin, OCT, Hex) 5 Binary Storage & Registers. Signed Binary Number representation, Signed Mag, R’s &(R-1)’s Complement 6 Signed Binary Addition and Subtraction. R’s Complement. Signed Binary Addition and Subtraction. (R-1)’s Complement 7 Codes.  BCD, Excess-3, Parity Bits, ASCII & Uni-Codes

 Unit II Binary Logic & Gates PDF 1 Binary logic and gates, Boolean Algebra, Basic identities of Boolean algebra. Algebraic manipulation, Complement of a function. 2 Canonical and Standard forms, Minterms and Maxterms, Sum of products and Products of Sums. 3 Physical properties of gates: fan-in, fan-out, propagation delay. Timing diagrams. Tri-state drivers. 4 Map method of simplification: Two-, Three-, and Four-variable K-Map. 5 Map manipulation: Essential prime implicants, Non-essential prime implicants, Simplification procedure, POS simplification, Don’t care conditions and simplification, Five, and Six-variable K-Map. 6 Universal gates; NAND, NOR gates: 2-level implementation. Multilevel Circuits. 7 Exclusive-OR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation and checking.

 Unit III Combinational Logic PDF 1 Combinational Logic, Design Procedure & Examples. 2 Half and Full Adders, Half and Full Subtractor, Ripple Carry Adder design and delay analysis 3 Carry Look-Ahead Adder, Binary Adder-Subtractor. BCD Adder, Binary Multiplier 4 MSI parts. Decoders, Decoder expansion,  combinational logic implementation using decoders, Encoders & Priority Encoders 5 Multiplexers, Function Implementation using multiplexers, Demultiplexers 6 Magnitude Comparator. 7 Examples of MSI designs

 Unit IV Sequential Circuits PDF 1 Sequential Circuits: Latches, Clocked latches: SR , D, T and JK. Race problem in clocked JK-Latch. Function & Excitation Tables of clocked latches: SR, D, and JK. 2 Flip-Flops: Master-Slave, T-FF. Function & Excitation Tables of T-FF. Asynchronous/Direct Clear and Set Inputs. Setup, Hold 3 Sequential Circuit Design: Excitation Tables. Design procedure, State diagrams and state tables. 4 Sequential Circuit Analysis: Input equations, State table. 5 Mealy vs. Moore models of FSMs. Examples.

Unit V

Registers & Counters

PDF

1

Registers, Registers with parallel load, Shift Registers. Bi-directional shift register.

2

#### Synchronous Binary Counters: Up-Down Counters.

3

Counters with Parallel  load, enable, synchronous clear and asynchronous clear. Use of available counters to build counters of different count.

4

Other counters: Ripple Counter, Arbitrary Count Sequence.

 Unit VI Memory & PLDs PDF 1 Memory devices: RAMs & ROMs . Combinational Circuit Implementation with ROM 2 Programmable Logic Devices: PLAs, PALs, FPGA’a

SOLUTION TO SELECTED TOPICS

HOMEWORK, QUIZ, EXAM AND THEIR SOLUTIONS

1. Homework 1 and its solution
2. Homework 2 and its solution
3. Homework 3  and its solution
4. Homework 4  and its solution
5. Quiz 1 and solution
6. Exam 1 and its solution
7. Exam 2 and its solution
8. Quiz 2 and solution
9. Quiz 3 and solution

SOFTWARE TOOLS FOR LOGIC DESIGN

A presentation was given to the students on how to use CAD tools for logic design (see lecture topics)

Students are encouraged to form teams of two for working on the course project listed here:

Design of an 8-Bit Magnitude Comparator using Logisim

Students are given the chance to improve their Exam II grades based on timely submission of their project report. The report must be written in a way to meet the Engineering Design Aspect at 200-level (see Guideline here).   The email of Mr. Abbasi is:

Ameer Ahmed Abbasi [ameer_abbasi@hussan.edu.sa]

Mr. Ameer Ahmed Abbasi  will be available for helping the students on Logisim on Monday, from 8 am to 9 am, 5th of January, 2008.

Project Supporting Material

Website for Logisim

Introductory Guidelines to Engineering Design

Guidelines to Engineering Design

Evaluation of Student Design is as follows:

 S.No. Student ID Documentation Circuit 1 200669580 Fair Fair 2 200576510 Vey Good Excellent 3 200670780 Vey Good Excellent 4 200628120 Poor Very Poor 5 200630980 Very Good Excellent 6 200684180 Excellent Excellent 7 200638480 Excellent Excellent 8 200639380 Fair Excellent 9 200645960 Very Poor Poor 10 200646060 Poor Excellent 11 200650940 Good Very Good 12 200652600 Fair Excellent 13 200660760 Very Poor Good 14 200667040 Good Excellent