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Project Title: Implementation of Some Routing Permutations in VLSI

Project Code: MAM3

The design of large scale high-speed switching devices requires that
many switching paths be activated and reserved in parallel within one
single VLSI chip.
The problem is to study the VLSI design approaches for the effective
implementation of some routing permutations in the case of large number of
links which are subject to some geometric arrangment along their paths.
Generally, the link permutations (geometric arrangments) are needed to
(1) interconnect successive switching stages and (2) some bus arrangements.
The student is to: (1) review current state of the art in multi-links
approaches (folding and routing), (2) identify a number of interesting
geometric link arrangments and routing permutations used in high speed
switching devices, and (3) carry out simulation of these folding and
routing arrangments by using some VLSI tools such as Magic.
Some of the relevant measure of performance would be: the achievability
of a given routing or folding and its geometric distribution, the length
of the links (longest and shortest) in a given arrangment, the associated
area, and the associated delays.
%H. M. Alnuweiri and Sadiq M. Sait. `Efficient Network Folding
%Techniques for Routing Permutations in VLSI'. IEEE Transactions on
%Very Large Scale Integrated (VLSI) Systems, June 1995, pp 254-263.

**Status Available **
**Name of Supervisor Dr. M. Al-Mouhamed and Dr. A. El-Maleh **
**Action Plan To be submitted **
**Progress Report To be submitted **
**Attendance Report Satisfactory **
**Student(s) None **
**Number of Semesters One or two **
**Co-requisite COE Course on VLSI
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